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1.发明申请公开(公告)号：US20190159369A1
公开(公告)日：2019-05-23
申请号：US16259442
申请日：2019-01-28
Inventor： Domenico Massimo Porto , Giovanni Luca Torrisi , Manuel Gaertner , Sergio Lecce
Abstract: A thermal control process for an electronic power device including a multi junction integrated circuit may include defining a first and at least one second groups of junctions, with each group including one first and at least one second junctions, and associating a thermal detector with each group. A first group control may be executed which detects group electric signals representative of the temperature detected by the thermal detectors, processes the group electric signals with reference to a group critical thermal event, identifies a critical group when the corresponding group electric signal detects the critical group thermal event, and generates group deactivating signals suitable for selectively deactivating the first and the at least one second junctions of the identified critical group with respect to the remaining junctions of the integrated circuit.
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公开(公告)号：US10257917B2
公开(公告)日：2019-04-09
申请号：US15957578
申请日：2018-04-19
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GmbH
Inventor： Philippe Sirito-Olivier , Giovanni Luca Torrisi , Manuel Gaertner , Fritz Burkhardt
Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.
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公开(公告)号：US11889594B2
公开(公告)日：2024-01-30
申请号：US17654532
申请日：2022-03-11
Applicant: STMicroelectronics (Grenoble 2) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GMBH
Inventor： Manuel Gaertner , Philippe Sirito-Olivier , Giovanni Luca Torrisi , Thomas Urbitsch , Christophe Roussel , Fritz Burkhardt
IPC: H05B45/14 , H05B45/46 , H05B45/50 , H05B45/325
CPC classification number: H05B45/46 , H05B45/14 , H05B45/325 , H05B45/50
Abstract: A system includes lighting devices coupled to output supply pins, a microcontroller circuit, and a driver circuit, which receives data therefrom, and switches coupled in series to the lighting devices. The driver circuit includes output supply pins and selectively propagates a supply voltage to the output supply pins to provide respective pulse-width modulated supply signals at the output supply pins. The driver circuit computes duty-cycle values of the pulse-width modulated supply signals as a function of the data received from the microcontroller circuit. The lighting devices include at least one subset coupled to the same output supply pin. The microcontroller individually controls the switches via respective control signals to individually adjust a brightness of the lighting devices in the at least one subset of lighting devices.
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公开(公告)号：US11823750B2
公开(公告)日：2023-11-21
申请号：US17244450
申请日：2021-04-29
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics S.r.l.
Inventor： Philippe Sirito-Olivier , Giovanni Luca Torrisi
CPC classification number: G11C16/3454 , G11C16/105 , G11C16/26 , G11C16/30 , G11C17/00
Abstract: A method for writing into a one-time programmable memory of an integrated circuit includes attempting, by a memory control circuit of the integrated circuit, to write data in at least one first register of the one-time programmable memory; verifying, by the memory control circuit, whether the data has been correctly written in the at least one first register; and, in case the data has not been correctly written in the at least one first register, attempting, by the memory control circuit, to write the data in at least one second register of the one-time programmable memory.
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公开(公告)号：US10917087B2
公开(公告)日：2021-02-09
申请号：US16719053
申请日：2019-12-18
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42 , G05F1/618 , G05F1/56 , H02J7/34
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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Patent Agency Ranking
公开(公告)号：US20190267991A1
公开(公告)日：2019-08-29
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G05B11/42 , G01R19/165
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US11372435B2
公开(公告)日：2022-06-28
申请号：US16804994
申请日：2020-02-28
Applicant: STMicroelectronics S.r.l.
Inventor： Giovanni Luca Torrisi , Salvatore Abbisso , Cristiano Meroni
Abstract: A voltage regulator circuit includes a first voltage regulator having a first output voltage selection pin set and producing a first output voltage based on a first digital signal received at the first output voltage selection pin set, and a second voltage regulator having a second output voltage selection pin set and producing a second output voltage based on a second digital signal received at the second output voltage selection pin set. The first and second voltage regulators are operable in a voltage tracking mode with the output voltage of the second voltage regulator tracking the output voltage of the first voltage regulator when digital signals received at the selection pin sets have a same value. An overvoltage sensor detects overvoltage events at the first voltage regulator. Control circuitry selectively avoids operation in voltage tracking mode as a result of an overvoltage event detected at the first voltage regulator.
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公开(公告)号：US11342908B2
公开(公告)日：2022-05-24
申请号：US17145863
申请日：2021-01-11
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Abstract: An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode.
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公开(公告)号：US20200287755A1
公开(公告)日：2020-09-10
申请号：US16800733
申请日：2020-02-25
Applicant: STMicroelectronics S.r.l.
Inventor： Domenico Massimo Porto , Giovanni Luca Torrisi , Ignazio Testoni
IPC: H04L25/03 , H03M1/12 , H04L12/40 , H04B17/345
Abstract: A method of compensating electromagnetic emissions of a device for use in a communication bus, the method including: transmitting a test signal over the communication bus; receiving, at the device, the test signal after propagation over the communication bus; performing frequency analysis processing of the test signal received to detect a set of harmonic components of the test signal received having an amplitude exceeding a certain threshold; storing respective values of frequency of harmonic components in the set of harmonic components having an amplitude exceeding the certain threshold; and generating and transmitting over the communication bus a set of compensation signals, each compensation signal in the set of compensation signals being a sinusoidal signal having a respective frequency equal to one of the frequencies stored, and being in anti-phase with respect to the harmonic component of the test signal received having the respective frequency.
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公开(公告)号：US10560092B2
公开(公告)日：2020-02-11
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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