公开(公告)号：US11798630B2

公开(公告)日：2023-10-24

申请号：US17407903

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Fabio Enrico Carlo Disegni ,  Chantal Auricchio ,  Cesare Torti ,  Davide Manfre' ,  Laura Capecchi ,  Emanuela Calvetti ,  Stefano Zanchi

IPC: G11C16/28 ,  G11C16/10 ,  G11C7/04 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C7/04 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

公开(公告)号：US20180151223A1

公开(公告)日：2018-05-31

申请号：US15639540

申请日：2017-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Cesare Torti ,  Fabio Enrico Carlo Disegni ,  Davide Manfre' ,  Massimo Fidone

IPC: G11C13/00 ,  H01L27/24

CPC classification number: G11C13/0028 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L29/7841 ,  H01L45/06

Abstract: A memory device includes an array of phase-change memory cells and a word line. The memory device includes a control circuit, a first pull-up MOSFET and a second pull-up MOSFET connected in series between a first power-supply node set at a first supply voltage and the word line, a first pull-down MOSFET and a second pull-down MOSFET connected in series between the word line and a second power-supply node set at a reference potential, and a biasing MOSFET connected between the word line and a third power-supply node set at a second supply voltage higher than the first supply voltage. The first and second pull-up MOSFETs and the first and second pull-down MOSFETs have breakdown voltages lower than the breakdown voltage of the biasing MOSFET.

公开(公告)号：US20190051348A1

公开(公告)日：2019-02-14

申请号：US16056818

申请日：2018-08-07

Applicant: STMicroelectronics S.r.l.

Inventor： Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfre'

IPC: G11C13/00

Abstract: According to one embodiment, a PCM memory device includes a memory matrix having memory cells of the phase-change type organized in a plurality of word lines and bit lines. Each memory cell has a storage element and an access element including at least one MOS transistor, which is controlled to allow access to the storage element and to carry out read/programming storage operations, in which source terminals of the MOS transistors of access elements of the memory cells of the same word line are connected to the same source line. The source lines of the memory matrix are electrically short-circuited in groups. A single source line driver element for each group of source lines is configured in such a manner as to generate a respective source line driver signal in order to bias in a corresponding manner all the source lines of the respective group.