公开(公告)号：US20230420557A1

公开(公告)日：2023-12-28

申请号：US18335916

申请日：2023-06-15

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Angelo MAGRI' ,  Stefania FORTUNA

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L21/765 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734

Abstract: A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.

公开(公告)号：US20210151599A1

公开(公告)日：2021-05-20

申请号：US17096697

申请日：2020-11-12

Applicant: STMicroelectronics S.r.l.

Inventor： Angelo MAGRI' ,  Stefania FORTUNA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/765 ,  H01L29/66

Abstract: A power MOSFET device includes an active area accommodating a first body region and a second body region having a first and, respectively, a second conductivity value. The second value is higher than the first value. A first channel region is disposed in the first body region between a first source region and a drain region, and the first channel region has and having a first channel length. A second channel region is disposed in the second body region between a second source region and the drain region, and the second channel region has and having a second channel length smaller than the first channel length. A first device portion, having a first threshold voltage, includes the first channel region, and a second device portion, having a second threshold voltage higher than the first threshold voltage, includes the second channel region.

公开(公告)号：US20140138739A1

公开(公告)日：2014-05-22

申请号：US14166075

申请日：2014-01-28

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Angelo MAGRI' ,  Antonino Sebastiano ALESSANDRIA ,  Stefania FORTUNA ,  Leonardo FRAGAPANE

IPC: H01L29/10 ,  H01L29/739

CPC classification number: H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

Abstract translation: 一种用于制造集成在半导体衬底上的功率器件的方法的实施例，至少包括以下步骤：在半导体衬底中至少形成具有侧壁和底部的沟槽，覆盖所述至少一个的侧壁和底部 沟槽，其具有第一绝缘涂层并且在所述至少一个沟槽内部形成导电栅极结构。 该方法的一个实施例提供了导电栅极结构的形成，包括以下步骤：用第一导电材料的第二导电涂层覆盖至少侧壁; 制造具有与第一导电材料不同的电阻率的第二导电材料的导电中心区域; 以及在所述第二导电涂层和所述导电中心区之间形成多个导电桥。