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    INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE HAVING AN IMPROVED TRENCH GATE STRUCTURE
    1.
    发明申请
    INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE HAVING AN IMPROVED TRENCH GATE STRUCTURE 审中-公开
    集成电源装置在具有改进的电镀门结构的半导体衬底上

    公开(公告)号：US20140138739A1

    公开(公告)日：2014-05-22

    申请号：US14166075

    申请日：2014-01-28

    申请人： STMICROELECTRONICS S.r.l.

    发明人： Angelo MAGRI' ,  Antonino Sebastiano ALESSANDRIA ,  Stefania FORTUNA ,  Leonardo FRAGAPANE

    IPC分类号： H01L29/10 ,  H01L29/739

    CPC分类号： H01L29/1037 ,  H01L29/405 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/4941 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

    摘要： An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region.

    摘要翻译： 一种用于制造集成在半导体衬底上的功率器件的方法的实施例，至少包括以下步骤：在半导体衬底中至少形成具有侧壁和底部的沟槽，覆盖所述至少一个的侧壁和底部 沟槽，其具有第一绝缘涂层并且在所述至少一个沟槽内部形成导电栅极结构。 该方法的一个实施例提供了导电栅极结构的形成，包括以下步骤：用第一导电材料的第二导电涂层覆盖至少侧壁; 制造具有与第一导电材料不同的电阻率的第二导电材料的导电中心区域; 以及在所述第二导电涂层和所述导电中心区之间形成多个导电桥。

    STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS
    4.
    发明申请
    STRUCTURE FOR HIGH VOLTAGE DEVICE AND CORRESPONDING INTEGRATION PROCESS 审中-公开
    高压器件结构与相应的集成工艺

    公开(公告)号：US20150349052A1

    公开(公告)日：2015-12-03

    申请号：US14824813

    申请日：2015-08-12

    申请人： STMICROELECTRONICS S.R.L.

    发明人： Mario Giuseppe SAGGIO ,  Domenico MURABITO ,  Angelo MAGRI'

    IPC分类号： H01L29/06 ,  H01L29/739 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/10

    CPC分类号： H01L29/0634 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7811

    摘要： An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.

    摘要翻译： 一种用于高压器件的结构的实施例，其包括至少半导体衬底被第一导电类型的外延层覆盖，其中实现了多个柱结构，哪些柱结构包括高纵横比深度 所述外延层又被活性表面积覆盖，其中所述高电压器件被实现，所述列结构中的至少一个外部部分又由第二导电类型的硅外延层实现，所述硅外延层相反 比所述第一类型的导电性和具有使在所述列结构之外的所述外延层中的掺杂剂电荷平衡的掺杂剂电荷以及在所述外部部分内部实现的电介质填充部分，以便完全填充所述深沟槽。

    VERTICAL-CONDUCTION INTEGRATED ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THEREOF
    7.
    发明申请
    VERTICAL-CONDUCTION INTEGRATED ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THEREOF 有权
    垂直导体集成电子器件及其制造方法

    公开(公告)号：US20140141603A1

    公开(公告)日：2014-05-22

    申请号：US14166522

    申请日：2014-01-28

    申请人： STMicroelectronics S.r.l.

    发明人： Ferruccio FRISINA ,  Mario Giuseppe SAGGIO ,  Angelo MAGRI'

    IPC分类号： H01L21/02 ,  H01L21/265

    CPC分类号： H01L29/7806 ,  H01L21/02573 ,  H01L21/046 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/0821 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7802 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

    摘要： An embodiment of a vertical-conduction integrated electronic device formed in a body of semiconductor material which includes: a substrate made of a first semiconductor material and with a first type of conductivity, the first semiconductor material having a first bandgap; an epitaxial region made of the first semiconductor material and with the first type of conductivity, which overlies the substrate and defines a first surface; and a first epitaxial layer made of a second semiconductor material, which overlies the first surface and is in direct contact with the epitaxial region, the second semiconductor material having a second bandgap narrower than the first bandgap. The body moreover includes a deep region of a second type of conductivity, extending underneath the first surface and within the epitaxial region.

    摘要翻译： 形成在半导体材料体内的垂直导电集成电子器件的实施例包括：由第一半导体材料制成并具有第一导电类型的衬底，第一半导体材料具有第一带隙; 由第一半导体材料制成并且具有第一类型的导电性的外延区域，其覆盖在衬底上并限定第一表面; 以及由第二半导体材料制成的第一外延层，其覆盖在第一表面上并与外延区直接接触，第二半导体材料具有比第一带隙窄的第二带隙。 身体还包括延伸在第一表面下方和外延区域内的第二类导电性的深区域。