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公开(公告)号：US20230127446A1
公开(公告)日：2023-04-27
申请号：US17963534
申请日：2022-10-11
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI
Abstract: A power switch current sensing circuit includes matching first and second transistors having sources connected to first and second terminals, respectively, of the power switch. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror sinks a current from the first node equal to a current flowing through the second transistor. A biasing circuit provides a same biasing voltage to the control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and the current sunk by the current mirror circuit from the first node flows through the output resistance. An output voltage produced at the first node is indicative of the current flowing through the power switch.
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2.发明申请公开(公告)号：US20160268887A1
公开(公告)日：2016-09-15
申请号：US15163394
申请日：2016-05-24
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
Abstract: An electrical-energy harvesting system envisages a transducer for converting energy from an environmental energy source into a transduced signal, an electrical energy harvesting interface for receiving the transduced signal and for supplying a harvesting signal, and an energy storage element coupled to the electrical energy harvesting interface for receiving the harvesting signal. The electrical-energy harvesting system also includes a voltage converter connected to the electrical energy harvesting interface for generating a regulated voltage. The harvesting interface samples an open-circuit voltage value of the transduced signal, generates an optimized voltage value starting from the open-circuit voltage value, and generates an upper threshold voltage and a lower threshold voltage on the basis of the optimized voltage value. The harvesting interface controls the voltage converter in switching mode so that the harvesting signal has a value between the upper and lower threshold voltages in at least one operating condition.
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3.发明申请公开(公告)号：US20230016168A1
公开(公告)日：2023-01-19
申请号：US17863828
申请日：2022-07-13
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Giuseppe CALDERONI
IPC: H02M3/158 , H02M1/00 , G09G3/3233
Abstract: A first node of converter circuit receives an input, provides an output at a second node, and has a third node coupled by an inductance to ground. A first switch has a current path between the first and third nodes and a second switch has a current path between the third and second nodes. The converter circuit operates in a first state (with the first switch conductive and the second switch non-conductive) and a second state (with the first switch non-conductive and the second switch conductive). Current flowing through the first switch is sensed during the first state to produce a sensing signal indicative of inductance current. The sensing signal is averaged to produce an averaged sensing signal indicative of an average value of the current. The averaged sensing signal is then weighted by a time during which the second switch is conductive to produce a weighted signal.
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公开(公告)号：US20210349491A1
公开(公告)日：2021-11-11
申请号：US17380542
申请日：2021-07-20
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Germano NICOLLINI
Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.
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公开(公告)号：US20190036518A1
公开(公告)日：2019-01-31
申请号：US16043346
申请日：2018-07-24
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Germano NICOLLINI
Abstract: A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.
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Patent Agency Ranking
公开(公告)号：US20230299670A1
公开(公告)日：2023-09-21
申请号：US18121767
申请日：2023-03-15
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI , Stefano RAMORINI
CPC classification number: H02M3/156 , H02M1/0003
Abstract: A switching DC-DC converter circuit includes a switching stage having an input node receiving an input voltage and an output node producing an output voltage. The converter includes feedback loop circuitry coupled to the output node of the switching stage to produce, at a respective output node, a control signal of the converter circuit as a function of a difference between the output voltage and a reference voltage. The converter includes test loop circuitry arranged between an output node of the feedback loop circuitry and the output node of the switching stage. The test loop, when enabled, sources a current to the output node of the switching stage or sinks a current from the output node of the switching stage as a function of a value of the control signal of the converter circuit. The feedback loop circuitry is calibrated during a test phase of the switching DC-DC converter circuit.
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公开(公告)号：US20210099087A1
公开(公告)日：2021-04-01
申请号：US17122132
申请日：2020-12-15
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
IPC: H02M3/158
Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.
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公开(公告)号：US20210067148A1
公开(公告)日：2021-03-04
申请号：US16559118
申请日：2019-09-03
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
Abstract: A DC-DC converter includes clock generation circuitry generating first and second clock signals that are out of phase, and a control signal generator generating a switching control signal at an edge of the second clock signal based upon a comparison of an error voltage to a summed voltage. Boost circuitry charges an energy storage component during an on-phase and discharges the energy storage component during an off-phase to thereby generate an output voltage. The on-phase and off-phase are set as a function of the switching control signal. Sum voltage generation circuitry generates a ramp voltage in response to an edge of the first clock signal and generates the summed voltage at an edge of the second clock signal. The sum voltage represents a sum of the ramp voltage and a voltage representative of the current flowing in the energy storage component during the on-phase.
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公开(公告)号：US20240154515A1
公开(公告)日：2024-05-09
申请号：US17980188
申请日：2022-11-03
Applicant: STMicroelectronics S.r.l.
Inventor： Marco ATTANASIO , Stefano RAMORINI
CPC classification number: H02M1/0025 , H02M3/04 , H03M1/1057 , H03M1/785
Abstract: A converter system includes a reference buffer buffering a reference input to produce a DAC reference, operating from a reference feedback voltage generated by a reference divider. A tail buffer generates a tail voltage from an input voltage generated from the DAC reference by a tail divider. An R-2R type DAC utilizes an R-2R ladder to generate a DAC output from a code. This ladder has a tail resistor coupled to the tail voltage. A feedback buffer buffers the DAC output to produce a converter reference. A DC-DC converter generates a DC output from a DC input, based upon a converter feedback voltage. A feedback divider coupled between the DC output and the converter reference generates the converter feedback voltage. Control circuitry selectively taps the reference divider to produce the reference feedback voltage (performing gain trimming) and selectively taps the tail divider to produce the input voltage (performing offset trimming).
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公开(公告)号：US20220166315A1
公开(公告)日：2022-05-26
申请号：US17533338
申请日：2021-11-23
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
IPC: H02M3/07
Abstract: Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.
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