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1.发明申请SYSTEM FOR DRIVING AN ARRAY OF MEMS STRUCTURES AND CORRESPONDING DRIVING METHOD 有权用于驱动MEMS结构阵列和相应驱动方法的系统公开(公告)号：US20150344295A1
公开(公告)日：2015-12-03
申请号：US14675230
申请日：2015-03-31
Applicant: STMICROELECTRONICS S.R.L.
IPC: B81B7/00
CPC classification number: B81B7/008 , B81B3/00 , B81B7/04 , B81B2201/0257 , B81B2207/03 , B81B2207/053 , H04R3/007 , H04R3/12 , H04R19/005 , H04R2201/003
Abstract: A system for driving a MEMS array having a number of MEMS structures, each defining at least one row terminal and one column terminal, envisages: a number of row driving stages, each for supplying row-biasing signals to the row terminal of each MEMS structure associated to a respective row; a number of column driving stages, each for supplying column-biasing signals to the column terminal of each MEMS structure associated to a respective column; and a control unit, for supplying row-address signals to the row driving stages for generation of the row-biasing signals and for supplying column-address signals to the column driving stages for generation of the column-biasing signals. The control unit further supplies row-deactivation and/or column-deactivation signals to one or more of the row and column driving stages, for causing deactivation of one or more rows and/or columns of the MEMS array.
Abstract translation: 用于驱动具有多个MEMS结构的MEMS阵列的系统，每个MEMS结构限定至少一个行端子和一个列端子，设想：多个行驱动级，每个用于向每个MEMS结构的行端子提供行偏置信号 相关联的行; 多个列驱动级，每个列驱动级用于向与各列相关联的每个MEMS结构的列端子提供列偏置信号; 以及控制单元，用于将行地址信号提供到行驱动级，用于产生行偏置信号，并将列地址信号提供给列驱动级，以产生列偏置信号。 控制单元还向行驱动级和列驱动级中的一个或多个驱动级提供行去激活和/或列停用信号，以使MEMS阵列的一个或多个行和/或列的去激活。
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公开(公告)号：US20210384830A1
公开(公告)日：2021-12-09
申请号：US17335523
申请日：2021-06-01
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
Abstract: A control circuit for controlling switching operation of a switching stage of a converter includes a phase detector circuit that generates a pulse-width modulated (PWM) signal in response to a phase comparison of two clock signals. A first clock signal has a frequency determined as a function of a first feedback signal proportional to converter output voltage. A first transconductance amplifier generates a first current indicative of a difference between a reference voltage and the first feedback signal, and a second transconductance amplifier generates a second current indicative of a difference between the reference voltage and a second feedback signal proportional to a derivative of the converter output voltage. A delay line introduces a delay in the first clock signal that is dependent on the first and second currents as well as a compensation current dependent on a selected operational mode of the converter.
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公开(公告)号：US20210184576A1
公开(公告)日：2021-06-17
申请号：US17117847
申请日：2020-12-10
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
Abstract: First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.
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公开(公告)号：US20210013808A1
公开(公告)日：2021-01-14
申请号：US16924410
申请日：2020-07-09
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI
Abstract: First and second FETs of a half-bridge are series connected between first and second terminals and are gate driven, respectively, by first and second drivers. An inductance is connected to the intermediate node of the half-bridge. Power supply for the second driver circuit is a supply voltage generated by a voltage regulator as a function of the voltage between the first and the second terminal. Power supply for the first driver circuit is a supply voltage generated by a bootstrap capacitor having a first terminal connected via a first switch to receive the supply voltage output from the voltage regulator and a second terminal connected to the intermediate node. The first terminal of the bootstrap capacitor is further connected by a second switch to receive a second supply voltage. A control circuit generates control signals for the first and second driver circuits and the first and second switches.
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公开(公告)号：US20210006163A1
公开(公告)日：2021-01-07
申请号：US16916335
申请日：2020-06-30
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI
Abstract: A first switch couples an input node receiving a main control signal for a main switching stage of a multi-phase converter to an output node delivering a secondary control signal for a secondary switching stage following actuation of the secondary switching stage. A second switch couples the output node to a capacitor during a time period of actuation/deactuation of the secondary switching stage. Current is sourced to the capacitor during the actuation time period or sunk from the capacitor during the deactuation time period. The sourced or sunk current may be generated proportional to the main control signal.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20160268887A1
公开(公告)日：2016-09-15
申请号：US15163394
申请日：2016-05-24
Applicant: STMICROELECTRONICS S.R.L.
Inventor： Stefano RAMORINI , Alessandro GASPARINI , Alberto CATTANI
Abstract: An electrical-energy harvesting system envisages a transducer for converting energy from an environmental energy source into a transduced signal, an electrical energy harvesting interface for receiving the transduced signal and for supplying a harvesting signal, and an energy storage element coupled to the electrical energy harvesting interface for receiving the harvesting signal. The electrical-energy harvesting system also includes a voltage converter connected to the electrical energy harvesting interface for generating a regulated voltage. The harvesting interface samples an open-circuit voltage value of the transduced signal, generates an optimized voltage value starting from the open-circuit voltage value, and generates an upper threshold voltage and a lower threshold voltage on the basis of the optimized voltage value. The harvesting interface controls the voltage converter in switching mode so that the harvesting signal has a value between the upper and lower threshold voltages in at least one operating condition.
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公开(公告)号：US20230299670A1
公开(公告)日：2023-09-21
申请号：US18121767
申请日：2023-03-15
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Alessandro GASPARINI , Stefano RAMORINI
CPC classification number: H02M3/156 , H02M1/0003
Abstract: A switching DC-DC converter circuit includes a switching stage having an input node receiving an input voltage and an output node producing an output voltage. The converter includes feedback loop circuitry coupled to the output node of the switching stage to produce, at a respective output node, a control signal of the converter circuit as a function of a difference between the output voltage and a reference voltage. The converter includes test loop circuitry arranged between an output node of the feedback loop circuitry and the output node of the switching stage. The test loop, when enabled, sources a current to the output node of the switching stage or sinks a current from the output node of the switching stage as a function of a value of the control signal of the converter circuit. The feedback loop circuitry is calibrated during a test phase of the switching DC-DC converter circuit.
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8.发明公开公开(公告)号：US20230163767A1
公开(公告)日：2023-05-25
申请号：US17982712
申请日：2022-11-08
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Alberto CATTANI , Alessandro GASPARINI
CPC classification number: H03L7/0991 , H03L7/091 , H03L7/10
Abstract: In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between first and second clock signals. The first and second clock signals are generated by first and second current-controlled oscillators, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, with the first and second currents applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to the control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively.
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公开(公告)号：US20230128113A1
公开(公告)日：2023-04-27
申请号：US17964420
申请日：2022-10-12
Applicant: STMicroelectronics S.r.l.
Inventor： Marco PINSERO , Marco ATTANASIO , Alberto CATTANI
IPC: H03K4/50
Abstract: In start-up, current is sourced by a current source to a first plate of a first capacitor while a second capacitor is maintained at zero charge. In a subsequent first operating phase, current is sourced to a first plate of the second capacitor while a second plate of the first capacitor is connected to the first plate of the second capacitor. At the end of the first operating phase, the first capacitor is discharged. In a subsequent second operating phase, current is sourced to the first plate of the first capacitor while a second plate of the second capacitor is connected to the first plate of the first capacitor. At the end of the second operating phase, the second capacitor is discharged. Steady state operation of the circuit involves an alternation of the first and second operating phases interleaved with transition phases where the first and second capacitors are discharged.
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公开(公告)号：US20210099087A1
公开(公告)日：2021-04-01
申请号：US17122132
申请日：2020-12-15
Applicant: STMicroelectronics S.r.l.
Inventor： Alberto CATTANI , Stefano RAMORINI , Alessandro GASPARINI
IPC: H02M3/158
Abstract: A half-bridge converter is controlled by a circuit including a differential circuit receiving a reference signal and a feedback signal which is a function of an output signal from the converter. The half-bridge converter includes high-side and low-side electronic switches. A comparator generates a PWM-modulated signal for controlling the converter as a function of the duty cycle of the PWM-modulated signal in response to a signal at an intermediate node between the high-side and low-side electronic switches and an output of the differential circuit. A gain circuit block coupled between the intermediate node and the input of the comparator applies a ramp signal to the input of the comparator which is a function of the signal at the intermediate node. A variable gain is applied by the gain circuit block in order to keep a constant value for the duty cycle of said PWM-modulated signal irrespective of converter operation.
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