公开(公告)号：US20230032898A1

公开(公告)日：2023-02-02

申请号：US17874595

申请日：2022-07-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Paolo Giuseppe CAPPELLETTI ,  Fausto PIAZZA ,  Andrea REDAELLI

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.

公开(公告)号：US20220238603A1

公开(公告)日：2022-07-28

申请号：US17581557

申请日：2022-01-21

Applicant: STMicroelectronics S.r.l.

Inventor： Paolo Giuseppe CAPPELLETTI ,  Andrea REDAELLI

IPC: H01L27/24 ,  H01L27/22

Abstract: An electronic cell includes an integrated stack of structures including, successively: a first electrode; an ovonic threshold switch layer below the first electrode; and a fixed resistor below the ovonic threshold switch layer. A second electrode may be included between fixed resistor and the ovonic threshold switch layer. A memory layer, for example a phase change material layer, a resistive random-access memory layer or a magneto-resistive random-access memory layer, may be included between the first electrode and the ovonic threshold switch layer.

公开(公告)号：US20230170022A1

公开(公告)日：2023-06-01

申请号：US17993118

申请日：2022-11-23

Applicant: STMicroelectronics S.r.l.

Inventor： Elisa PETRONI ,  Andrea REDAELLI

IPC: G11C13/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C13/0069 ,  H01L45/126 ,  H01L45/144 ,  H01L45/06

Abstract: A phase change memory element has a memory region, a first electrode and a second electrode. The memory region is arranged between the first and the second electrodes and has a bulk zone and an active zone. The memory region is made of a germanium, antimony and tellurium based alloy, wherein germanium is in a higher percentage than antimony and tellurium in the bulk zone of the memory region. The active zone is configured to switch between a first stable state associated with a first memory logic level and a second stable state associated with a second memory logic level. The active zone has, in the first stable state, a uniform, amorphous structure and, in the second stable state, a differential polycrystalline structure including a first portion, having a first stoichiometry, and a second portion, having a second stoichiometry different from the first stoichiometry.

公开(公告)号：US20230240160A1

公开(公告)日：2023-07-27

申请号：US18099528

申请日：2023-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： Mario ALLEGRA ,  Andrea REDAELLI

IPC: H10N70/00 ,  H10N70/20

CPC classification number: H10N70/8413 ,  H10N70/231 ,  H10N70/011

Abstract: A phase-change memory cell includes a heater, a memory region made of a phase-change material located above said heater, and an electrically conductive element positioned adjacent to the memory region and the heater at a first side of the heater. The electrically conductive element extends parallel to a first axis and has, parallel to the first axis, a first dimension at the first side that is greater than a second dimension at a second side opposite to the first side.