公开(公告)号：US20230032898A1

公开(公告)日：2023-02-02

申请号：US17874595

申请日：2022-07-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Paolo Giuseppe CAPPELLETTI ,  Fausto PIAZZA ,  Andrea REDAELLI

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.

公开(公告)号：US20210057426A1

公开(公告)日：2021-02-25

申请号：US17092551

申请日：2020-11-09

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto PIAZZA ,  Sebastien LAGRASTA ,  Raul Andres BIANCHI ,  Simon JEANNOT

IPC: H01L27/11546 ,  H01L21/28 ,  H01L27/06 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/11521 ,  H01L29/49 ,  H01L29/66

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

公开(公告)号：US20230058720A1

公开(公告)日：2023-02-23

申请号：US17885406

申请日：2022-08-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvie DEL MEDICO ,  Jean-Christophe GRENIER ,  Jean-Christophe GIRAUDIN ,  Philippe KOWALCZYK ,  Fausto PIAZZA

IPC: H01L23/00 ,  H01L21/027

Abstract: The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.

公开(公告)号：US20230006132A1

公开(公告)日：2023-01-05

申请号：US17847016

申请日：2022-06-22

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent FAVENNEC ,  Fausto PIAZZA

IPC: H01L45/00 ,  H01L27/24 ,  H01L23/522

Abstract: A method for making a phase change memory includes a step of forming an array of phase change memory cells, with each cell being separated from neighboring cells in the same line of the array and from neighboring cells in the same column of the array, by the same first distance. The method further includes a step of etching one memory cell out of N, with N being at least equal to 2, in each line or each column.

公开(公告)号：US20180233511A1

公开(公告)日：2018-08-16

申请号：US15954874

申请日：2018-04-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Fausto PIAZZA ,  Sebastien LAGRASTA ,  Raul Andres BIANCHI ,  Simon JEANNOT

IPC: H01L27/11546 ,  H01L29/66 ,  H01L21/02 ,  H01L29/49 ,  H01L49/02 ,  H01L27/11521 ,  H01L27/06 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/11541

Abstract: An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.