公开(公告)号：US20210175422A1

公开(公告)日：2021-06-10

申请号：US17112842

申请日：2020-12-04

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique Et Aux Energies Alternatives

Inventor： Jean-Philippe REYNARD ,  Sylvie DEL MEDICO ,  Philippe Brun

IPC: H01L45/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01L27/24

Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.

公开(公告)号：US20230058720A1

公开(公告)日：2023-02-23

申请号：US17885406

申请日：2022-08-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvie DEL MEDICO ,  Jean-Christophe GRENIER ,  Jean-Christophe GIRAUDIN ,  Philippe KOWALCZYK ,  Fausto PIAZZA

IPC: H01L23/00 ,  H01L21/027

Abstract: The present description relates to a method of manufacturing an interconnection structure of an integrated circuit intended to be encapsulated in an encapsulation resin in contact with a first surface of a protection layer. The protection layer is resting on a first surface of the interconnection structure. The interconnection structure comprising copper interconnection elements extending at least partly through an insulating layer and flush with the first surface of said interconnection structure. The manufacturing method includes a step of structuring of the protection layer or a step of forming of the protection layer with a structuring. The structuring step or the forming step is adapted to structuring the first surface of the protection layer in the form of an alternation of ridges and troughs.

公开(公告)号：US20230361064A1

公开(公告)日：2023-11-09

申请号：US18311779

申请日：2023-05-03

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Marion CROISY ,  Sylvie DEL MEDICO

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/05 ,  H01L23/3192 ,  H01L21/56 ,  H01L24/13 ,  H01L24/45 ,  H01L2224/05647 ,  H01L2224/04042 ,  H01L2224/0401 ,  H01L2224/13147 ,  H01L2224/45147

Abstract: The present description relates to a method of manufacturing an end of an interconnection structure of an integrated circuit, the method including: providing an integrated circuit including an interconnection structure including copper interconnection elements at least partly extending through an insulating layer and flush with a first surface of said interconnection structure; forming a protection layer on the first surface of the interconnection structure, said protection layer including a material adapted to protecting the copper of the interconnection elements; forming a passivation layer on the protection layer, the passivation layer having a first thickness; and forming a first opening in the passivation layer across a second thickness smaller than the first thickness, to keep a residual passivation layer at the bottom of the first opening.

公开(公告)号：US20230247919A1

公开(公告)日：2023-08-03

申请号：US18296331

申请日：2023-04-05

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMicroelectronics (Crolles 2) SAS

Inventor： Jean-Philippe REYNARD ,  Sylvie DEL MEDICO ,  Philippe Brun

IPC: H10N70/00 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/20

CPC classification number: H10N70/011 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/80 ,  H10N70/231 ,  H10N70/826

Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.