公开(公告)号：US12051745B2

公开(公告)日：2024-07-30

申请号：US17614253

申请日：2020-11-20

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Yi Gong ,  Wei Liu ,  Zhendong Mao ,  Zhenyi Xu

IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/423 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66734

摘要： A gate trench and a source trench are formed simultaneously in the same etching process, a p-type semiconductor layer and a p-type doped region can be contacted in a self-aligned manner in the source trench, and the process is simple. A first insulating layer and a first gate are formed in a lower part of the gate trench, and a second insulating layer and a second gate are formed in an upper part of the gate trench so that the thick first insulating layer can protect the second gate from being easily broken down, the first gate can increase an electric field near a bottom of the gate trench, and thus a voltage withstand level of the semiconductor device can be improved. A bottom of the source trench can penetrate deep into a second n-type semiconductor layer.

公开(公告)号：US11658209B2

公开(公告)日：2023-05-23

申请号：US17611419

申请日：2020-09-22

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Wei Liu ,  Lei Liu ,  Rui Wang ,  Yi Gong

IPC分类号： H01L21/02 ,  H01L29/06 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308

CPC分类号： H01L29/0634 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/26513 ,  H01L21/3081 ,  H01L21/30604

摘要： Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

公开(公告)号：US11211485B2

公开(公告)日：2021-12-28

申请号：US16475728

申请日：2018-10-29

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Zhendong Mao ,  Yuanlin Yuan ,  Lei Liu ,  Wei Liu ,  Rui Wang ,  Yi Gong

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

摘要： Provided is a trench-type power transistor. The trench-type power transistor includes a source, a drain, a first gate, a second gate, a body diode and a body region contact diode. The body diode and the body region contact diode are connected in series. The first gate controls turn-on and turn-off of a first current channel through a gate voltage, the second gate is connected to the source and controls turn-on and turn-off of a second current channel through a source voltage.

公开(公告)号：US11081574B2

公开(公告)日：2021-08-03

申请号：US16627675

申请日：2018-10-29

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Wei Liu ,  Yuanlin Yuan ,  Lei Liu ,  Rui Wang ,  Yi Gong

IPC分类号： H01L29/739 ,  H03K17/567

摘要： Disclosed is an insulated gate bipolar transistor (IGBT) power device, including a bipolar transistor, a first MOS transistor, a second MOS transistor, a body diode and a body region contact diode. An anode of the body region contact diode and an anode of the body diode are connected to the bipolar transistor. A first gate of the first MOS transistor is externally connected to a gate voltage of the IGBT power device and configured to control turning on and off of the first MOS transistor by means of the gate voltage of the IGBT power device. A second gate of the second MOS transistor is connected to an emitter voltage of the IGBT power device and configured to control turning on and off of the second MOS transistor by means of the emitter voltage of the IGBT power device.

公开(公告)号：US20210036135A1

公开(公告)日：2021-02-04

申请号：US16966071

申请日：2019-01-30

申请人： Suzhou Oriental Semiconductor Co., Ltd.

发明人： Wei Liu ,  Lei Liu ,  Zhendong Mao ,  Yuanlin Yuan

IPC分类号： H01L29/739 ,  H01L29/66 ,  H01L29/08 ,  H01L29/417

摘要： Provided is an IGBT power device. The device includes: a p-type collector region; an n-type drift region located above the p-type collector region; multiple first grooves, where a second groove is provided below each of the multiple first grooves; a gate structure located in the first groove and the second groove; a p-type body region located between two adjacent first grooves; an n-type emitter region located in the p-type body region; and an n-type hole charge blocking region located between two adjacent second grooves.

公开(公告)号：US10411116B2

公开(公告)日：2019-09-10

申请号：US15532530

申请日：2016-04-08

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO.,LTD

发明人： Lei Liu ,  Yuanlin Yuan ,  Pengfei Wang ,  Wei Liu ,  Yi Gong

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10

摘要： The present disclosure relates to the technical field of semiconductor power devices, and in particular relates to a semiconductor super-junction power device and a manufacturing method therefor. The super-junction power device of the present disclosure includes a termination region and a cell region; the cell region includes a substrate epitaxial layer and a drain region at a bottom of the substrate epitaxial layer, the substrate epitaxial layer has a plurality of pillar epitaxial doped regions and a plurality of JFET regions, a body region is arranged at a top of each of the plurality of pillar epitaxial doped regions; the body regions have at least two unequal widths; two source regions are arranged in each of the body regions; a gate oxide layer is arranged on the body regions and the JFET regions; and a gate is arranged on the gate oxide layer.

公开(公告)号：US12094929B2

公开(公告)日：2024-09-17

申请号：US17440557

申请日：2020-09-28

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Yi Gong ,  Wei Liu ,  Zhendong Mao ,  Zhenyi Xu

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/78

CPC分类号： H01L29/0661 ,  H01L29/063 ,  H01L29/407 ,  H01L29/7813

摘要： The present application belongs to the technical field of semiconductor power devices and provides a semiconductor power device. The semiconductor power device includes an n-shaped substrate, an n-shaped epitaxial layer positioned on the n-shaped substrate, and at least three grooves recessed inside the n-shaped epitaxial layer, where a portion of the n-shaped epitaxial layer between two adjacent grooves of the at least three grooves is a mesa structure, an upper part of the mesa structure is provided with a p-shaped body region, and an n-shaped source region is provided inside the p-shaped body region. The mesa structure includes at least one mesa structure with a lower width being a first width and at least one mesa structure with a lower width being a second width, and the second width is greater than the first width.

公开(公告)号：US11973107B2

公开(公告)日：2024-04-30

申请号：US17621486

申请日：2020-11-10

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Wei Liu ,  Yuanlin Yuan ,  Rui Wang ,  Lei Liu

IPC分类号： H01L29/06 ,  H01L21/308 ,  H01L29/78

CPC分类号： H01L29/0634 ,  H01L21/3086 ,  H01L29/7813

摘要： A manufacturing method of a semiconductor super-junction device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer and a second insulating layer as a mask to form a second groove in the n-type substrate. A gate structure is formed in the second groove.

公开(公告)号：US11908889B2

公开(公告)日：2024-02-20

申请号：US17428137

申请日：2019-12-05

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Yi Gong ,  Wei Liu ,  Yuanlin Yuan ,  Lei Liu ,  Rui Wang

IPC分类号： H01L29/06 ,  H01L27/06 ,  H01L29/88 ,  H01L29/78 ,  H01L29/788

CPC分类号： H01L29/0634 ,  H01L27/0629 ,  H01L29/788

摘要： Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

公开(公告)号：US11626480B2

公开(公告)日：2023-04-11

申请号：US17440078

申请日：2020-09-22

申请人： SUZHOU ORIENTAL SEMICONDUCTOR CO., LTD.

发明人： Wei Liu ,  Yuanlin Yuan ,  Zhenyi Xu ,  Yi Gong

IPC分类号： H01L21/3065 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308

摘要： Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a p-type column is formed through an epitaxial process, and then a gate is formed in a self-alignment manner.