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1.发明授权Parallel pseudo-random generator for emulating a serial pseudo-random generator and method for carrying out same 失效用于仿真串行伪随机发生器的并行伪随机发生器及其执行方法
公开(公告)号：US5031129A
公开(公告)日：1991-07-09
申请号：US351175
申请日：1989-05-12
CPC分类号： H04L25/03872
摘要： A parallel pseudo-random generator emulates a serial pseudo-random generator which in turn is defined by a polynomial of the type 1+x.sup.M + . . . +x.sup.P ; that is, wherein the serial outputs are generated such that the next serial output value is based upon an Exclusive OR combination of at least two preceding serial output values. The parallel pseudo-random generator comprises latches and Exclusive OR gates, the number of latches and Exclusive OR gates each being at least equal to the polynomial order of the serial pseudo-random generator defining polynomial. The outputs of the latches represent the outputs of the parallel pseudo-random generator and may be used to scramble data on parallel data lines. A method is disclosed for determining the interconnects between the latch outputs and the Exclusive OR gate inputs based upon the number of latches and the serial pseudo-random generator defining polynomial.
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公开(公告)号：US5528530A
公开(公告)日：1996-06-18
申请号：US371884
申请日：1995-01-12
CPC分类号： H04Q11/0414 , H04J3/076 , H04J2203/0003
摘要： A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information. The desynchronizer utilizes a leak filter (26) having a linear branch (54) and an integrator branch (56), both branches having adjustable factors (61, 63, 65, 88, 90, 91, 93, 95, 100, 102, 105) regarding their operation, wherein the adjustable factors are selected depending upon threshold values (86, 87, 89, 62) which in turn are based upon the difference between the average write address and read address for the associated elastic store (22) within which the incoming data removed from the synchronous communication system frame is temporarily stored. The leak filter (26) forms part of a phase locked loop which in turn adjusts the read clock frequency (46) in a manner which minimizes overflow or underflow of the elastic store while simultaneously minimizing the rate of change of the read clock rate so as to limit jitter. A fault recovery apparatus forms part of the desynchronizer for enabling fastlock high gain factors (67, 97, 107) to quickly adjust the read clock when elastic store overflow or underflow occurs. The gain factors associated with both the linear branch and integrator branch are provisionable (118, 120) as well as elastic store size and thresholds resulting in a desynchronizer which can be modified to meet the particular jitter requirements of a particular synchronous communication system. A calculation engine (82) performs iterative calculations to generate the leak filter output value using a reduced number of logic gates for ASIC implementation.
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3.发明授权Parallel bit detection circuit for detecting frame synchronization information imbedded within a serial bit stream and method for carrying out same 失效用于检测在串行数据流中发生的帧同步信息的并行比特检测电路及其执行方法
公开(公告)号：US5081654A
公开(公告)日：1992-01-14
申请号：US351723
申请日：1989-05-12
CPC分类号： H04J3/0608 , H04J2203/0089 , H04L2012/5672
摘要： A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.
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4.发明授权Desynchronizer for adjusting the read data rate of payload data received over a digital communication network transmitting payload data within frames 失效用于调整通过数字通信网络接收的有效载荷数据的读取数据速率的同步器，其在帧内传送有效载荷数据
公开(公告)号：US5404380A
公开(公告)日：1995-04-04
申请号：US935020
申请日：1992-08-25
CPC分类号： H04J3/076
摘要： A desynchronizer for processing pointer movements and stuff bit information associated with payload data transmitted within a synchronous digital communication network. The desynchronizer includes a payload extractor (58) for removing payload data and storing it in an elastic store (32). The extractor also removes the pointer and stuff bit information which is passed through a digital low pass bit leaking module (36). The difference between the write and read addresses of the elastic store is determined (modules 48 and 50) and algebraically combined with the output of the bit leaking module (36) so as to provide the necessary data for adjusting the instantaneous frequency of a variable controlled oscillator (44) that generates the timing base for the read clock for reading the payload from the elastic store in a manner that minimizes jitter.
摘要翻译： 用于处理与同步数字通信网络内发送的有效载荷数据相关联的指针移动和填充比特信息的去同步器。 去同步器包括用于去除有效载荷数据并将其存储在弹性存储器（32）中的有效载荷提取器（58）。 提取器还去除通过数字低通位泄漏模块（36）的指针和填充位信息。 确定弹性存储器的写入和读取地址之间的差异（模块48和50），并且与位泄漏模块（36）的输出代数组合，以便提供用于调整变量控制的瞬时频率的必要数据 振荡器（44），其以使抖动最小化的方式生成用于从弹性存储器读取有效载荷的读取时钟的定时基准。
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公开(公告)号：US5402452A
公开(公告)日：1995-03-28
申请号：US935008
申请日：1992-08-25
CPC分类号： H04Q11/0414 , H04J3/076 , H04J2203/0003
摘要： A desynchronizer (20) for desynchronizing data stored within synchronous payload envelopes of a synchronous communication protocol such as SONET (Synchronous Optical Network), provides for smoothing the periodically discontinuous clock signal associated with that data after the synchronous communication protocol overhead has been removed. The desynchronizer accommodates for shifts in the position of the payload envelope and hence, the data within the synchronous communication frame as well as adjustments within the data itself due to asynchronous bit stuff information. The desynchronizer utilizes a leak filter (26) having a linear branch (54) and an integrator branch (56), both branches having adjustable factors (61, 63, 65, 88, 90, 91, 93, 95, 100, 102, 105) regarding their operation, wherein the adjustable factors are selected depending upon threshold values (86, 87, 89, 62) which in turn are based upon the difference between the average write address and read address for the associated elastic store (22) within which the incoming data removed from the synchronous communication system frame is temporarily stored. The leak filter (26) forms part of a phase locked loop which in turn adjusts the read clock frequency (46) in a manner which minimizes overflow or underflow of the elastic store while simultaneously minimizing the rate of change of the read clock rate so as to limit jitter. A fault recovery apparatus forms part of the desynchronizer for enabling fastlock high gain factors (67, 97, 107) to quickly adjust the read clock when elastic store overflow or underflow occurs. The gain factors associated with both the linear branch and integrator branch are provisionable (118, 120) as well as elastic store size and thresholds resulting in a desynchronizer which can be modified to meet the particular jitter requirements of a particular synchronous communication system. A calculation engine (82) performs iterative calculations to generate the leak filter output value using a reduced number of logic gates for ASIC implementation.
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公开(公告)号：US5185736A
公开(公告)日：1993-02-09
申请号：US351861
申请日：1989-05-12
申请人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
发明人： Raymond E. Tyrrell , O. Lamar Bishop , William E. Powell , Dale L. Krisher , William H. Stephenson , M. Rodney Briscoe , Hal A. Thorne , Claude M. Hurlocker , V. Paul Runyon , Timothy J. Williams , Joseph E. Sutherland , William B. Weeber , Michael J. Gingell , Kenneth J. Stoia , William J. Fox , Jeffrey P. Jones , Richard M. Czerwiec , Ertugrul Baydar , Heinrich T. Sonnenberg , Richard Peters , Gus C. Sanders , Richard J. Sanders, Jr. , Francis G. Noser , Joseph L. Smith , Jak Yaemsiri , Camille A. Abu-Saba , Patrick M. Farrell , Wenkwei Rou , Victor W. Wilkerson , Mohammad S. Arani , Stephen C. Dunning , Keith Bernhardt , Dana Merrill , Michael Sutton
CPC分类号： H04J3/1611 , H04J3/08 , H04J2203/0048 , H04J2203/006
摘要： A synchronous optical transmission system for interfacing SONET formatted channels to lower speed channels in either a SONET format or otherwise. The transmission system incorporates a fiber transmission system, terminal multiplexers and add/drop multiplexers that in turn incorporate a plurality of features, such as parallel scrambling circuitry, frame synchronization circuitry and the like.
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7.发明授权Low jitter timing recovery technique and device for asynchronous transfer mode (ATM) constant bit rate (CBR) payloads 失效低抖动定时恢复技术和异步传输模式（ATM）恒定比特率（CBR）有效载荷的设备
公开(公告)号：US6111878A
公开(公告)日：2000-08-29
申请号：US963786
申请日：1997-11-04
申请人： William E. Powell
发明人： William E. Powell
CPC分类号： H04J3/0632 , H04L2012/5616 , H04L2012/5654 , H04L2012/5674
摘要： 052440872 An existing synchronous residual time stamp (SRTS) algorithm (76, 78, 80, 82, 106, 104) is used in conjunction with adaptively filtered buffer fill information (74) to reconstruct an original constant bit rate (CBR) payload clock rate (102) for asynchronous transfer mode (ATM) CBR payloads (88, 96). The SRTS time stamp (96) is used as the primary factor used to recover the payload clock rate, but a secondary payload frequency correction factor (112) is generated by filtering (118, 120) the desynchronizer buffer fill position. This correction factor is determined as part of a feedback arrangement which adaptively (128) alters the filtering time constant based on the offset position of the buffer from its center. In this way, payload clock frequency (102) is corrected, even in the presence of loss of synchronization PRS traceability between mapping and desynchronizer nodes to keep the desynchronizer buffer from overflowing.
摘要翻译： 052440872现有的同步残留时间戳（SRTS）算法（76,78,80,82,106,104）与自适应滤波的缓冲器填充信息（74）结合使用以重构原始恒定比特率（CBR）有效载荷时钟速率 （102）用于异步传输模式（ATM）CBR有效载荷（88,96）。 使用SRTS时间戳（96）作为用于恢复有效载荷时钟速率的主要因素，但是通过对（118,120）去同步器缓冲器填充位置进行滤波（118,120）来产生辅助有效载荷频率校正因子（112）。 该校正因子被确定为反馈装置的一部分，其自适应地（128）基于缓冲器从其中心的偏移位置来改变滤波时间常数。 以这种方式，即使存在映射和去同步器节点之间的同步PRS可追溯性的存在，校正了有效载荷时钟频率（102），以保持不同步缓冲器不溢出。
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公开(公告)号：US4116565A
公开(公告)日：1978-09-26
申请号：US799944
申请日：1977-05-24
IPC分类号： G01N27/447 , G01N27/26
CPC分类号： G01N27/44721
摘要： An analyzer for electrophoretic samples has a sample stage movable linearly with respect to a source and a detector of analysis energy. During a first scan of the sample, a voltage is produced representing either the minimum detected fluorescence or the minimum detected optical density. During a second scan, the voltage is combined with the output of the detector to automatically correct the output to a reference.
摘要翻译： 用于电泳样品的分析器具有相对于源线和可分析能量检测器的样品台。 在样品的第一次扫描期间，产生表示检测到的最小荧光或最小检测光密度的电压。 在第二次扫描期间，电压与检测器的输出相结合，以将输出自动校正为参考。
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公开(公告)号：US5708687A
公开(公告)日：1998-01-13
申请号：US674422
申请日：1996-07-02
CPC分类号： H03L7/1978 , H03L7/0994 , H03L7/1806 , H03L7/235 , H04L7/0331 , H04L7/0334
摘要： Digital signal processing techniques are used to synthesize a range of output frequencies locked to a non-pullable reference oscillator, and the synthesized output frequency is used in a slave low bandwidth phase-locked loop; by increasing digital resolution in a phase accumulation register, any desired resolution of output frequencies can be generated. The range of output frequencies is synthesized in such a way as to generate only high-frequency jitter, which can be easily filtered by follow-on, low-cost, relatively high bandwidth phase-locked loops which are typically needed for frequency multiplication in a given system. The magnitude of residual jitter is easily controlled by proper choice of the non-pullable oscillator reference frequency, the output frequency range to be synthesized and various other digital factors, such as divider ratios. Improved noise performance is achieved while still maintaining a wide pulling range of the composite phase-locked loop.
摘要翻译： 数字信号处理技术用于合成锁定到不可引用参考振荡器的输出频率范围，合成输出频率用于从低带宽锁相环; 通过在相位累积寄存器中增加数字分辨率，可以产生任何期望的输出频率分辨率。 输出频率的范围被合成为仅产生高频抖动，其可以容易地通过后续，低成本，相对高带宽的锁相环来滤波，这通常是在 给定系统。 通过适当选择不可取的振荡器参考频率，要合成的输出频率范围和各种其他数字因数（如分频比）可以容易地控制剩余抖动的幅度。 在保持复合锁相环宽范围的同时，实现了改进的噪声性能。
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公开(公告)号：US5349310A
公开(公告)日：1994-09-20
申请号：US74060
申请日：1993-06-09
CPC分类号： H03L7/1978 , H03L7/1806 , H03L7/185
摘要： The circuit arrangement of the invention presents an oscillator, whose frequency can be linearly varied within a wide control range, without affecting the oscillator's stability. The frequency of a fixed frequency generator (1) is divided to the desired frequency by a frequency divider (2), whose divider ratio can be varied in very small steps, and the resulting jitter is filtered out by a very simple phase control circuit (3). Improved short-term stability and holdover performance are also achieved. The oscillator can be universally used as clock generator in all digital circuit arrangements.
摘要翻译： 本发明的电路装置提供一种振荡器，其频率可以在宽的控制范围内线性变化，而不影响振荡器的稳定性。 固定频率发生器（1）的频率由分频器（2）分成期望的频率，其分频比可以非常小的步长变化，并且所产生的抖动由非常简单的相位控制电路（ 3）。 改善短期稳定性和保持性能也得以实现。 振荡器可以被普遍用作所有数字电路布置中的时钟发生器。
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