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1.发明授权Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue 有权用于快速确定非移动指令队列中最旧指令的装置，系统和方法公开(公告)号：US07302553B2
公开(公告)日：2007-11-27
申请号：US10351556
申请日：2003-01-23
申请人： Sam Gat-Shang Chu , Hung Qui Le , Dung Quoc Nguyen
发明人： Sam Gat-Shang Chu , Hung Qui Le , Dung Quoc Nguyen
CPC分类号： G06F9/3836 , G06F9/3855 , G06F9/3857
摘要： An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.
摘要翻译： 提供了一种用于快速确定处理器的非移动指令队列中的最旧指令的装置，系统和方法。 特别地，在不移动队列中，以时钟周期一次存储指令。 在每个时钟周期，记录队列中的指令的当前状态。 结合队列中的指令的当前状态结合先前记录的指令状态，确定队列中最早的指令。 队列中的指令的状态包括是否已经发出指令执行，以及是否知道发出的指令已被接受执行。
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2.发明授权Apparatus and method for speeding up access time of a large register file with wrap capability 有权用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法公开(公告)号：US07243209B2
公开(公告)日：2007-07-10
申请号：US11044449
申请日：2005-01-27
CPC分类号： G06F9/30141 , G06F9/30098
摘要： An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
摘要翻译： 提供了一种用于加速具有包装能力的大型寄存器文件的访问时间的装置和方法。 利用该装置和方法，从电路配置中消除了传统寄存器文件系统中的2：1多路复用器，而是提供了一半地址的附加主复用器，例如寄存器堆的前四个子阵列， 需要包装能力。 这些附加的主多路复用器接收读地址和移位的读字线信号。 另一个主复用器接收读地址和未移位的读字线信号。 来自移位和未移位的主复用器的输出被提供给一组次级多路复用器，它们将来自移位和未移位的主复用器的输出的比特复用以产生要由多个读/写寄存器堆使用的读地址 系统。
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3.发明授权Apparatus and method for providing multiple reads/writes using a 2Read/2Write register file array 有权使用2Read / 2Write寄存器文件阵列提供多次读/写的装置和方法公开(公告)号：US07663963B2
公开(公告)日：2010-02-16
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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4.发明申请Apparatus and Method for Providing Multiple Reads/Writes Using a 2Read/2Write Register File Array 有权使用2Read / 2Write寄存器文件阵列提供多个读/写的装置和方法公开(公告)号：US20080239860A1
公开(公告)日：2008-10-02
申请号：US12134537
申请日：2008-06-06
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供一种用于读取多个连续条目并使用2Read / 2Write寄存器文件仅写入一个读取地址和一个写入地址的多个连续条目的装置和方法。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 该装置和方法提供了通过仅对一个地址进行4到16个解码来写入连续条目的机制。 此外，该装置和方法提供了一种用于使用起始读字地址和基于起始读字地址生成的两个读字线从寄存器堆数组读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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5.发明授权Method for providing multiple reads/writes using a 2read/2write register file array 有权使用2read / 2write寄存器文件阵列提供多次读/写的方法公开(公告)号：US07400548B2
公开(公告)日：2008-07-15
申请号：US11054276
申请日：2005-02-09
IPC分类号： G11C8/00
CPC分类号： G06F9/30141
摘要： Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
摘要翻译： 提供了使用2Read / 2Write寄存器文件读取多个连续条目并且仅写入一个读取地址和一个写入地址的多个连续条目。 在一个示例性实施例中，64个入口寄存器文件阵列被划分为四个子阵列。 每个子阵列包含16个具有一个或多个2Read / 2Write SRAM单元的条目。 还提供了通过仅对一个地址进行4至16个解码来写入连续条目的机制。 此外，提供了一种用于使用起始读取字地址和基于起始读取字地址生成的两个读取字线从寄存器堆栈数据读取数据的机制。 两条读字线用于访问子阵列中条目的两个读端口。
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公开(公告)号：US07551475B2
公开(公告)日：2009-06-23
申请号：US11278439
申请日：2006-04-03
申请人： Vikas Agarwal , Sam Gat-Shang Chu , Hung Qui Le
发明人： Vikas Agarwal , Sam Gat-Shang Chu , Hung Qui Le
CPC分类号： G01R31/318541
摘要： A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to a higher order cell. The circuit may be copied as a series of cells wherein a bit held in each first-type cell is copied to the next higher second-type cell.
摘要翻译： 电路允许用户呈现信号以控制从第一型电池到第二型电池的数据流。 电路容易单独加载每个单元，以及通过将低阶单元的串行扫描输入到高阶单元来加载单元。 电路可以被复制为一系列单元，其中保持在每个第一类型单元中的位复制到下一较高的第二类型单元。
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公开(公告)号：US06901546B2
公开(公告)日：2005-05-31
申请号：US09876753
申请日：2001-06-07
申请人： Sam Gat-Shang Chu , Joachim Gerhard Clabes , Michael Normand Goulet , Johnny J. Leblanc , James Douglas Warnock
发明人： Sam Gat-Shang Chu , Joachim Gerhard Clabes , Michael Normand Goulet , Johnny J. Leblanc , James Douglas Warnock
IPC分类号： G01R31/317 , G01R31/3185 , G01R31/3187 , G06F11/27 , G01R31/28 , G06R11/00
CPC分类号： G01R31/3187 , G01R31/31705 , G01R31/318502 , G06F11/27
摘要： A device for fault testing in a microprocessor chip provides a LBIST circuit which has a first reference signature. A loading unit is further provided for receiving and outputting a set of masking data. A file unit connected to the loading unit is yet further provided for receiving the masking data. A masking unit connected to the file unit is yet further provided for generating a second reference signature based on the masking data from the file unit and a scanning data from a scan string in the chip. And, a signature logic connected to the output of the masking unit is yet further provided for compressing the second reference signature and inputting the compressed second reference signature to the LBIST circuit, wherein the compressed second reference signature replaces the first reference signature.
摘要翻译： 用于微处理器芯片中的故障测试的装置提供具有第一参考标识的LBIST电路。 进一步提供加载单元，用于接收和输出一组屏蔽数据。 还提供连接到加载单元的文件单元用于接收掩蔽数据。 还提供连接到文件单元的掩蔽单元，用于基于来自文件单元的掩蔽数据和来自芯片中的扫描串的扫描数据来生成第二参考签名。 并且，还提供连接到屏蔽单元的输出的签名逻辑，用于压缩第二参考签名并将压缩的第二参考签名输入到LBIST电路，其中压缩的第二参考签名替换第一参考签名。
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8.发明授权公开(公告)号：US06825691B1
公开(公告)日：2004-11-30
申请号：US10455163
申请日：2003-06-05
IPC分类号： H03K19173
CPC分类号： G11C11/4125
摘要： According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.
摘要翻译： 根据一种形式，锁存器具有输出节点和副组。 这些副组件各自具有耦合到输入电路的输出节点和耦合到重叠器输出节点的反馈电路，用于加强子锁的输出信号。 这些集合可操作以在它们各自的输入电路处接收数据信号，并在它们各自的输出节点上产生输出信号。 至少一个子批输出节点耦合到锁存器输出节点。 其他的一些子实体的输出节点连接在锁存器中，使得如果任何一个子实体受到辐射引起的状态的错误改变，则其他子集合的输出信号会减小锁存器输出信号的变化的影响 。 锁存器还包括多个扫描模式控制开关，其耦合到用于扫描数据的一个或多个子集。
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公开(公告)号：US6052008A
公开(公告)日：2000-04-18
申请号：US892861
申请日：1997-07-14
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
摘要翻译： 逻辑电路包括用于产生来自另一逻辑电路的输出信号的补码以输入到动态逻辑电路的反相器。 在动态逻辑电路的预充电和评估阶段期间，动态逻辑电路能够接收补码信号和动态输入信号。 允许补码信号在这样的阶段期间从低电平切换到高电平和高电平，而动态逻辑电路仍然能够正确地评估动态逻辑电路在补码信号上的逻辑运算 和动态输入信号。 p沟道FET耦合在内部预充电节点和p型沟道FET器件的栅电极接收补码信号的电压参考源之间。 这种配置消除了生成用于由动态逻辑电路使用的补码信号所需的重复电路的需要，并且还消除了当使用由简单反演产生的补码信号时防止潜在的错开关所必需的时钟偏移的相加。
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公开(公告)号：US5852373A
公开(公告)日：1998-12-22
申请号：US723814
申请日：1996-09-30
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.
摘要翻译： 动态逻辑电路能够在逻辑电路的预充电和评估阶段期间接收动态和静态输入信号，并且静态输入信号被允许从低电平切换到高电平和高电平 在这种阶段期间的低电平，并且逻辑电路仍然能够正确评估对静态和动态输入信号的实现的逻辑运算。 这通过在内部预充电节点和PFET器件的栅电极接收静态输入信号的电压参考源之间耦合PFET来实现。
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