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公开(公告)号：US6052008A
公开(公告)日：2000-04-18
申请号：US892861
申请日：1997-07-14
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit includes an inverter for generating a complement of an output signal from another logic circuit for input to a dynamic logic circuit. The dynamic logic circuit is capable of receiving both the complement signal and dynamic input signals during both the precharge and evaluate phases of the dynamic logic circuit. The complement signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages with the dynamic logic circuit still capable of correctly evaluating the implemented logical operation of the dynamic logic circuit on the complement signal and the dynamic input signals. A p-channel FET is coupled between the internal precharge node and a voltage reference source where the gate electrode of the p-channel FET device receives the complement signal. Such a configuration eliminates the need for duplicate circuitry necessary to generate the complement signal for use by the dynamic logic circuit and also eliminates the addition of clock skew necessary to prevent potential false switching when using a complement signal generated by simple inversion.
摘要翻译： 逻辑电路包括用于产生来自另一逻辑电路的输出信号的补码以输入到动态逻辑电路的反相器。 在动态逻辑电路的预充电和评估阶段期间，动态逻辑电路能够接收补码信号和动态输入信号。 允许补码信号在这样的阶段期间从低电平切换到高电平和高电平，而动态逻辑电路仍然能够正确地评估动态逻辑电路在补码信号上的逻辑运算 和动态输入信号。 p沟道FET耦合在内部预充电节点和p型沟道FET器件的栅电极接收补码信号的电压参考源之间。 这种配置消除了生成用于由动态逻辑电路使用的补码信号所需的重复电路的需要，并且还消除了当使用由简单反演产生的补码信号时防止潜在的错开关所必需的时钟偏移的相加。
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2.发明授权公开(公告)号：US06825691B1
公开(公告)日：2004-11-30
申请号：US10455163
申请日：2003-06-05
IPC分类号： H03K19173
CPC分类号： G11C11/4125
摘要： According to one form, a latch has an output node and sublatches. The sublatches each have an output node coupled to input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and to generate output signals on their respective output nodes. At least one sublatch output node is coupled to the latch output node. The output nodes of other ones of the sublatches are connected in the latch such that if any one of the sublatches is subjected to a radiation induced erroneous change of state the output signals of the other sublatches reduce an effect of the change on the latch output signal. The latch also includes a number of scanning-mode control switches coupled to ones of the sublatches for scanning data in or out.
摘要翻译： 根据一种形式，锁存器具有输出节点和副组。 这些副组件各自具有耦合到输入电路的输出节点和耦合到重叠器输出节点的反馈电路，用于加强子锁的输出信号。 这些集合可操作以在它们各自的输入电路处接收数据信号，并在它们各自的输出节点上产生输出信号。 至少一个子批输出节点耦合到锁存器输出节点。 其他的一些子实体的输出节点连接在锁存器中，使得如果任何一个子实体受到辐射引起的状态的错误改变，则其他子集合的输出信号会减小锁存器输出信号的变化的影响 。 锁存器还包括多个扫描模式控制开关，其耦合到用于扫描数据的一个或多个子集。
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公开(公告)号：US5852373A
公开(公告)日：1998-12-22
申请号：US723814
申请日：1996-09-30
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A dynamic logic circuit is capable of receiving both dynamic and static input signals during both the precharge and evaluate phases of the logic circuit, and the static input signal is permitted to switch from both a low level to a high level and a high level to a low level during such stages and the logic circuit is still capable of correctly evaluating the implemented logical operation on the static and dynamic input signals. This is performed in CMOS by coupling a PFET between the internal precharge node and a voltage reference source where the gate electrode of the PFET device receives the static input signal.
摘要翻译： 动态逻辑电路能够在逻辑电路的预充电和评估阶段期间接收动态和静态输入信号，并且静态输入信号被允许从低电平切换到高电平和高电平 在这种阶段期间的低电平，并且逻辑电路仍然能够正确评估对静态和动态输入信号的实现的逻辑运算。 这通过在内部预充电节点和PFET器件的栅电极接收静态输入信号的电压参考源之间耦合PFET来实现。
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公开(公告)号：US07142463B2
公开(公告)日：2006-11-28
申请号：US11242376
申请日：2005-10-03
IPC分类号： G11C7/10
CPC分类号： G11C7/22
摘要： A register file method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.
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5.发明授权Register file apparatus and method incorporating read-after-write blocking using detection cells 失效使用检测单元的注册文件装置和包含读写后封锁的方法公开(公告)号：US07012839B1
公开(公告)日：2006-03-14
申请号：US10922247
申请日：2004-08-19
IPC分类号： G11C5/02
CPC分类号： G11C7/22
摘要： A register file apparatus and method incorporating read-after-write blocking using detection cells provides improved read access times in high performance register files. One or more detection cells identical to the register file cells and located in the register file array are used to control the read operation in the register file by configuring the detection cells to either alternate value at each write or change to a particular value after a write and then detecting when the write has completed by detecting the state change of an active detection cell. The state change detection can be used to delay the leading edge of a read strobe or may be used in the access control logic to delay generation of a next read strobe. The register file thus provides a scalable design that does not have to be tuned for each application and that tracks over voltage and clock skew variation.
摘要翻译： 使用检测单元结合读写后阻塞的寄存器文件装置和方法在高性能寄存器文件中提供改进的读访问时间。 与寄存器文件单元相同并且位于寄存器文件阵列中的一个或多个检测单元用于通过将检测单元配置为在写入时的交替值或在写入之后变为特定值来控制寄存器文件中的读取操作 然后通过检测有源检测单元的状态变化来检测写入是否已经完成。 状态改变检测可以用于延迟读选通脉冲的前沿，或者可以在访问控制逻辑中使用以延迟下一个读选通脉冲的产生。 寄存器文件因此提供了一种可扩展的设计，不需要针对每个应用进行调整，并且跟踪过电压和时钟偏移变化。
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公开(公告)号：US06934181B2
公开(公告)日：2005-08-23
申请号：US10361200
申请日：2003-02-06
IPC分类号： G11C7/00 , G11C11/00 , G11C11/412
CPC分类号： G11C11/412
摘要： A method and memory array for reducing sub-threshold leakage in a memory array. A memory array may include a plurality of rows where each row may include one or more groups of cells. Within each group of cells, each cell may be coupled to a ground path and to a power path. A device, e.g., n-type transistor, p-type transistor, may be coupled to either the ground or power path in each group of cells thereby permitting the passing of the sub-threshold leakage from those cells in that group through the device. Consequently, the sub-threshold leakage in the memory array may be reduced.
摘要翻译： 一种用于减少存储器阵列中的次阈值泄漏的方法和存储器阵列。 存储器阵列可以包括多行，其中每行可以包括一个或多个单元组。 在每个单元组内，每个单元可以耦合到接地路径和功率路径。 诸如n型晶体管p型晶体管的器件可以耦合到每组单元中的接地或电源通路，从而允许从该组中的那些单元通过器件传递子阈值泄漏。 因此，可以减少存储器阵列中的次阈值泄漏。
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公开(公告)号：US06914450B2
公开(公告)日：2005-07-05
申请号：US10703016
申请日：2003-11-06
IPC分类号： G06F7/38 , G11C7/10 , H03K19/0175 , H03K19/173
CPC分类号： G11C7/1048 , G11C2207/007
摘要： A register-file bit read apparatus includes a decoder operable to receive a number of address-bit signals and responsively assert a select signal on one of M select lines. Each select line corresponds to a respective one of M register-file cells. The apparatus also includes a multiplexer having Q output nodes and M selectors. Each selector is coupled to one of the select lines and that select line's corresponding register-file cell. The selectors are in Q groups, each coupled to a respective one of the multiplexer's output nodes. The apparatus also includes an output logic gate having Q inputs, coupled to respective ones of the multiplexer output nodes. The multiplexer includes Q pull-ups, each of which is coupled to a respective one of the multiplexer output nodes and is operable to drive its multiplexer output node responsive to one of the address-bit signals.
摘要翻译： 寄存器 - 文件位读取装置包括：解码器，可操作用于接收多个地址位信号，并响应地在M个选择行之一中断言选择信号。 每个选择行对应于M个寄存器文件单元中的相应一个。 该装置还包括具有Q个输出节点和M个选择器的多路复用器。 每个选择器耦合到选择线之一，并选择线对应的寄存器文件单元。 选择器处于Q组中，每组耦合到多路复用器的输出节点中的相应一个。 该装置还包括具有Q输入的输出逻辑门，耦合到多路复用器输出节点中的相应一个。 多路复用器包括Q个上拉，其中每个Q上拉耦合到多路复用器输出节点中的相应一个，并且可操作以响应于地址位信号之一驱动其多路复用器输出节点。
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公开(公告)号：US06826090B1
公开(公告)日：2004-11-30
申请号：US10455161
申请日：2003-06-05
IPC分类号： G11C700
摘要： In one form of the invention, a radiation resistant latch has an overall output node, and first, second and third sublatches. The sublatches each have input circuitry, an output node coupled to the sublatch's input circuitry and feedback circuitry coupled to the sublatch's output node for reinforcing an output signal of the sublatch. The sublatches are operable to receive a data signal at their respective input circuitry and responsively generate binary-state output signals on their respective output nodes. The first and second sublatches are coupled to the third sublatch and the third sublatch has its output signal coupled to the overall output node such that if any one of the three sublatches is subjected to a radiation induced erroneous change of state, the output signals of the other two sublatches reduce an effect of the third sublatch feedback circuitry on an overall output signal for the latch.
摘要翻译： 在本发明的一种形式中，耐辐射闩锁具有总输出节点以及第一，第二和第三子实体。 这些分样具有输入电路，耦合到分页输入电路的输出节点和耦合到分页输出节点的反馈电路，用于加强子画面的输出信号。 这些副作用可操作以在它们各自的输入电路处接收数据信号，并在其各自的输出节点上响应地产生二进制状态输出信号。 第一和第二子集合被耦合到第三子交集，并且第三子选项具有耦合到整个输出节点的输出信号，使得如果三个子集合中的任何一个受到辐射引起的状态的错误改变，则输出信号 其他两个分样可以减少第三个分支反馈电路对锁存器的总输出信号的影响。
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9.发明授权Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation 失效动态静态逻辑控制元件，用于发出控制信号结束与逻辑评估之间的间隔公开(公告)号：US07015723B2
公开(公告)日：2006-03-21
申请号：US10922271
申请日：2004-08-19
IPC分类号： H03K19/00
CPC分类号： H03K19/0963
摘要： A dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation provides a compact circuit for blocking the indication of a non-evaluated state of a dynamic logic gate until a control signal has ended. The control signal is connected to a precharge input of the control element and a summing node is connected to one or more evaluation trees and to the control element output via an inverter. The inverter is connected to an override circuit that forces the output of the control element to a state opposite the precharge state until the control signal has ended. The output of the control element then assumes a state corresponding to the precharge state until an evaluation occurs. The control element output thus produces a window signal indicating the interval between the end of the control signal and the evaluation.
摘要翻译： 用于发信号通知控制信号的结束与逻辑评估之间的间隔的动态静态逻辑控制元件提供紧凑的电路，用于阻止动态逻辑门的未评估状态的指示，直到控制信号结束为止。 控制信号连接到控制元件的预充电输入，并且求和节点经由逆变器连接到一个或多个评估树和控制元件输出。 逆变器连接到超控电路，其将控制元件的输出强制到与预充电状态相反的状态，直到控制信号结束。 然后，控制元件的输出呈现与预充电状态相对应的状态，直到评估发生。 因此，控制元件输出产生指示控制信号的结束与评估之间的间隔的窗口信号。
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公开(公告)号：US07002860B2
公开(公告)日：2006-02-21
申请号：US10703017
申请日：2003-11-06
CPC分类号： G11C7/1012 , G11C7/1051 , G11C8/10
摘要： A bit-read apparatus includes a first decoder and N multiplexers, each having Q output nodes and Q pull-ups coupled thereto. Respective multiplexers have M selectors coupled to N×M respective select lines and register-file cells. The selectors are in Q groups coupled to respective output nodes. Each multiplexer has a logic gate with inputs coupled to respective multiplexer output nodes. A second decoder is coupled to an N+1th multiplexer having R output nodes and R pull-ups coupled thereto. The N+1th multiplexer also has N selectors, coupled to respective select lines of the second decoder and respective output logic gates of the N multiplexers. The N selectors are in R groups coupled to the R nodes. An output logic gate for N+1th multiplexer has R inputs coupled respectively to the R nodes. Each pull-up of the multiplexers drives its respective multiplexer output node responsive to an address-bit signal.
摘要翻译： 位读取装置包括第一解码器和N个多路复用器，每个具有与其耦合的Q个输出节点和Q个上拉电路。 各个复用器具有耦合到NxM个选择线和寄存器文件单元的M个选择器。 选择器处于耦合到相应输出节点的Q组中。 每个复用器具有逻辑门，其输入耦合到相应的多路复用器输出节点。 第二解码器耦合到具有耦合到其上的R个输出节点和R个上拉的第N + 1个多路复用器。 第N + 1个多路复用器还具有N个选择器，耦合到第二解码器的相应选择线和N个多路复用器的相应输出逻辑门。 N个选择器位于耦合到R个节点的R组中。 用于N + 1个多路复用器的输出逻辑门分别具有分别耦合到R个节点的R个输入。 多路复用器的每个上拉响应地址位信号驱动其相应的多路复用器输出节点。
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