公开(公告)号：US20240338297A1

公开(公告)日：2024-10-10

申请号：US18244677

申请日：2023-09-11

Applicant: SambaNova Systems, Inc.

Inventor： Arnav GOEL ,  Qi ZHENG ,  Guoyao FENG ,  Chen YANG ,  Jianding LUO

IPC: G06F11/36 ,  G06F15/78

CPC classification number: G06F11/3644 ,  G06F11/3636 ,  G06F15/7871

Abstract: A data processing system includes an array of reconfigurable units and a compiler configured to generate one or more configuration files for an application for execution on one or more reconfigurable processors. The data processing system further includes an execution flow logic which is configured to cause execution of the configuration files on the reconfigurable processors to be dependent upon one or more breakpoint conditions. The data processing further includes a runtime logic configured to execute the configuration files depending upon the breakpoint conditions. A corresponding method is also disclosed herein.

公开(公告)号：US20230251989A1

公开(公告)日：2023-08-10

申请号：US18107994

申请日：2023-02-09

Applicant: SambaNova Systems, Inc.

Inventor： Subhra MAZUMDAR ,  Guoyao FENG ,  Neal SANGHVI

IPC: G06F13/40 ,  G06F13/38 ,  G06F12/06

CPC classification number: G06F13/4022 ,  G06F13/382 ,  G06F12/0653 ,  G06F2213/3808 ,  G06F2213/0026

Abstract: A data processing system is presented that includes multiple local buses, a host processor, a network interface controller (NIC) for connecting to external storage via a network, one or more reconfigurable processors, and a bus switch. The bus switch couples the multiple local busses, thereby operatively coupling the one or more reconfigurable processors, the host processor, and the NIC. The one or more reconfigurable processors are configured to implement a virtual function that uses a virtual address for a memory access operation. The host processor is configured to implement an application programming interface (API) that translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct data access operation at the external storage that moves data directly between the one or more reconfigurable processors and the external storage, wherein the data bypasses the host processor.

公开(公告)号：US20240273057A1

公开(公告)日：2024-08-15

申请号：US18635114

申请日：2024-04-15

Applicant: SambaNova Systems, Inc.

Inventor： Greg DYKEMA ,  Maran WILSON ,  Guoyao FENG ,  Kuan ZHOU ,  Tianyu SUN ,  Taylor LEE ,  Kin Hing LEUNG ,  Arnav GOEL ,  Conrad Alexander TURLIK ,  Milad SHARIF

IPC: G06F15/80 ,  G06F8/41 ,  G06F15/78

CPC classification number: G06F15/8038 ,  G06F8/443 ,  G06F8/447 ,  G06F8/45 ,  G06F15/7867 ,  G06F15/80

Abstract: A host system for executing an application on first and/or second reconfigurable processors is presented. The host system is operatively coupled to the first and second reconfigurable processors, whereby the first reconfigurable processors have a first architecture, and the second reconfigurable processors have a second architecture that is different than the first architecture. The host system allocates reconfigurable processors of the first and/or second reconfigurable processors for executing the application and includes an auto-discovery module that is configured to determine whether the allocated reconfigurable processors include at least one of the first reconfigurable processors.

公开(公告)号：US20240231903A1

公开(公告)日：2024-07-11

申请号：US18614639

申请日：2024-03-23

Applicant: SambaNova Systems, Inc.

Inventor： Qi ZHENG ,  Arnav GOEL ,  Conrad Alexander TURLIK ,  Guoyao FENG ,  Joshua Earle POLZIN ,  Fansheng CHENG ,  Ravinder KUMAR ,  Greg DYKEMA ,  Subhra MAZUMDAR ,  Milad SHARIF ,  Jiayu BAI ,  Neal SANGHVI ,  Arjun SABNIS ,  Letao CHEN

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3877

Abstract: In a computer-implemented method a Dynamic Transfer Engine (DTE) included in a computing system receives a dynamic stimulus associated with transfer of stage data during execution of a dataflow application by the system. The DTE determines, based on source and destination devices of the transfer, a transfer method and a transfer channel to transfer the stage data between memories coupled to the source and destination devices. The DTE acquires, hardware resources of the computing system to transfer the stage using the channel and, initiates the transfer. A computer program product can cause one or more processors to perform the method. A computing system can comprise source and destination processors and memories, hardware channels to transfer data between the memories, a resource manager, and a DTE configured to perform the method.