公开(公告)号：US20230205613A1

公开(公告)日：2023-06-29

申请号：US18087104

申请日：2022-12-22

Applicant: SambaNova Systems, Inc.

Inventor： Joshua POLZIN ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Qi ZHENG ,  Maran WILSON ,  Neal SANGHVI

IPC: G06F9/54 ,  G06F9/50

CPC classification number: G06F9/544 ,  G06F9/5016

Abstract: A method of pipelining execution stages of a pipelined application can comprise a Buffer Pipeline Manager (BPM) of a Buffer Pipelined Application computing System (BPAS) allocating pipeline buffers, configuring access to the pipeline buffers by stage processors of the system, transferring buffers from one stage processor to a successor stage processor, and transferring data from a buffer in one memory to a buffer in an alternative memory. The BPM can allocate the buffers based on execution parameters associated with the pipelined application and/or stage processors. The BPM can transfer data to a buffer in an alternative memory based on performance, capacity, and/or topological attributes of the memories and/or processors utilizing the memories. The BPM can perform operations of the method responsive to interfaces of a Pipeline Programming Interface (PPI). A BPAS can comprise hardware processors, physical memories, stage processors, an application execution program, the PPI, and the BPM.

公开(公告)号：US20230205585A1

公开(公告)日：2023-06-29

申请号：US18084013

申请日：2022-12-19

Applicant: SambaNova Systems, Inc.

Inventor： Ranen CHATTERJEE ,  Ravinder KUMAR ,  Raghunath SHENBAGAM ,  Maran WILSON ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Arjun SABNIS ,  Yannan CHEN

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/54 ,  G06F13/40

CPC classification number: G06F9/5016 ,  G06F9/545 ,  G06F9/30123 ,  G06F13/4059 ,  G06F2209/5011

Abstract: A data processing system includes a runtime processor and a pool of reconfigurable data flow resources with memory units, busses, and arrays of physical configurable units. The runtime processor is operatively coupled to the pool of reconfigurable data flow resources and configured to load first and second configuration files for executing first and second user applications on first and second subsets of the arrays of physical configurable units and to assign first and second subsets of the memory units to the first and second user applications. The runtime processor starts execution of the first and second user applications on the first and second subsets of the arrays of physical configurable units, prevents the first user application from accessing the resources allocated to the second user application, and prevents the second user application from accessing resources allocated to the first user application.

公开(公告)号：US20240202046A1

公开(公告)日：2024-06-20

申请号：US18083403

申请日：2022-12-16

Applicant: SambaNova Systems, Inc.

Inventor： Anand MISRA ,  Conrad Alexander TURLIK ,  Maran WILSON ,  Anand VAYYALA ,  Raghu SHENBAGAM ,  Ranen CHATTERJEE ,  Pushkar Shridhar NANDKAR ,  Shivam RAIKUNDALIA

IPC: G06F9/50 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F9/5077 ,  G06F9/5016 ,  G06F13/4081 ,  G06F13/4221 ,  G06F2209/5011

Abstract: A data processing system comprises a pool of reconfigurable data flow resources with arrays of physical configurable units, a controller, and a runtime processor. The controller is configured to generate a hot-plug event in response to detecting a removal of an unallocated array of physical configurable units from the pool of reconfigurable data flow resources. The runtime processor is configured to execute user applications on a subset of the arrays of physical configurable units and to receive the hot-plug event from the controller. The runtime processor is further configured to make the removed unallocated array of physical configurable units unavailable for subsequent allocations of subsequent virtual data flow resources and subsequent executions of subsequent user applications, while the subset of the arrays of physical configurable units continues the execution of the user applications.

公开(公告)号：US20230244515A1

公开(公告)日：2023-08-03

申请号：US18118410

申请日：2023-03-07

Applicant: SambaNova Systems, Inc.

Inventor： Manish K. SHAH ,  Paul JORDAN ,  Maran WILSON ,  Ravinder KUMAR

IPC: G06F9/455 ,  G06F9/48

CPC classification number: G06F9/45558 ,  G06F9/4812 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: A system is presented that includes a communication link, a runtime processor, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes first and second dies arranged in a package, having respective first and second arrays of coarse-grained reconfigurable (CGR) units, and respective first and second communication link interfaces coupled to the communication link. The runtime processor is adapted for configuring the first and second communication link interfaces to provide access to the first and second arrays of coarse-grained reconfigurable units from first and second physical function drivers and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the first or to the second physical function driver and for sending the interrupt to a virtual function driver of the at least one virtual function driver.

公开(公告)号：US20240273057A1

公开(公告)日：2024-08-15

申请号：US18635114

申请日：2024-04-15

Applicant: SambaNova Systems, Inc.

Inventor： Greg DYKEMA ,  Maran WILSON ,  Guoyao FENG ,  Kuan ZHOU ,  Tianyu SUN ,  Taylor LEE ,  Kin Hing LEUNG ,  Arnav GOEL ,  Conrad Alexander TURLIK ,  Milad SHARIF

IPC: G06F15/80 ,  G06F8/41 ,  G06F15/78

CPC classification number: G06F15/8038 ,  G06F8/443 ,  G06F8/447 ,  G06F8/45 ,  G06F15/7867 ,  G06F15/80

Abstract: A host system for executing an application on first and/or second reconfigurable processors is presented. The host system is operatively coupled to the first and second reconfigurable processors, whereby the first reconfigurable processors have a first architecture, and the second reconfigurable processors have a second architecture that is different than the first architecture. The host system allocates reconfigurable processors of the first and/or second reconfigurable processors for executing the application and includes an auto-discovery module that is configured to determine whether the allocated reconfigurable processors include at least one of the first reconfigurable processors.

公开(公告)号：US20230244462A1

公开(公告)日：2023-08-03

申请号：US18118428

申请日：2023-03-07

Applicant: SambaNova Systems, Inc.

Inventor： Manish K. SHAH ,  Paul JORDAN ,  Maran WILSON ,  Ravinder KUMAR

IPC: G06F8/41 ,  G06F13/24

CPC classification number: G06F8/457 ,  G06F13/24 ,  G06F8/441 ,  G06F2213/0026

Abstract: A system is presented that includes a communication link, a runtime processor coupled to the communication link, and a reconfigurable processor. The reconfigurable processor is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes multiple arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the multiple arrays of coarse-grained reconfigurable units from a physical function driver and from at least one virtual function driver, and the reconfigurable processor is adapted for sending the interrupt to the physical function driver and to a virtual function driver of the at least one virtual function driver within the runtime processor.

公开(公告)号：US20230305881A1

公开(公告)日：2023-09-28

申请号：US18104759

申请日：2023-02-01

Applicant: SambaNova Systems, Inc.

Inventor： Manish K. SHAH ,  Paul JORDAN ,  Maran WILSON ,  Ravinder KUMAR

IPC: G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: A data processing system is presented that includes a communication link, a runtime processor, and one or more reconfigurable processors. A reconfigurable processor includes first and second dies arranged in a package, having respective K and L arrays of coarse-grained reconfigurable (CGR) units, and respective first and second communication link interfaces coupled to the communication link. The runtime processor is adapted for configuring the first communication link interface to provide access to the K arrays of CGR units through the communication link from a first physical function driver and from up to M virtual function drivers, and for configuring the second communication link interface to provide access to the K arrays of CGR units of the first die and to the L arrays of CGR units of the second die through the communication link from a second physical function driver and from up to N virtual function drivers.

公开(公告)号：US20230244461A1

公开(公告)日：2023-08-03

申请号：US18104758

申请日：2023-02-01

Applicant: SambaNova Systems, Inc.

Inventor： Manish K. SHAH ,  Paul JORDAN ,  Maran WILSON ,  Ravinder KUMAR

IPC: G06F8/41 ,  G06F13/24

CPC classification number: G06F8/457 ,  G06F8/441 ,  G06F13/24 ,  G06F2213/0026

Abstract: A data processing system is presented that includes a communication link, a runtime processor coupled to the communication link, and one or more reconfigurable processors. A reconfigurable processor of the one or more reconfigurable processors is adapted for generating an interrupt to the runtime processor in response to a predetermined event and includes arrays of coarse-grained reconfigurable (CGR) units and an interface to the communication link that couples the reconfigurable processor to the runtime processor via the communication link. The runtime processor is adapted for configuring the interface to the communication link to provide access to the arrays of CGR units through the communication link from a physical function driver and from a virtual function driver.

公开(公告)号：US20230205614A1

公开(公告)日：2023-06-29

申请号：US18087125

申请日：2022-12-22

Applicant: SambaNova Systems, Inc.

Inventor： Joshua POLZIN ,  Conrad Alexander TURLIK ,  Arnav GOEL ,  Qi ZHENG ,  Maran WILSON ,  Neal SANGHVI

IPC: G06F9/54

CPC classification number: G06F9/544

Abstract: A method of pipelining execution stages of a pipelined application comprises an application execution program (AEP) utilizing a Pipeline Programming Interface (PPI) of a Buffer Pipelined Application computing System (BPAS). In the method the AEP uses one interface of the PPI to determine buffers, among a set of pipeline buffers stored in physical memories of the BPAS, for the BPAS to execute operations a computing application using batches of application data. The AEP uses a second interface of the PPI to load data batches into pipeline buffers, and a third interface of the PPI to input the buffers to the BPAS for executing operations of the application. The AEP can use another interface of the PPI to allocate the buffers in particular physical memories of the BPAS. A computing system can comprise the AEP and BPAS, and can perform the method.