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    INTEGRATED CIRCUIT THAT MITIGATES INDUCTIVE-INDUCED VOLTAGE DROOP USING COMPUTE UNIT GROUP IDENTIFIERS
    4.
    发明公开
    INTEGRATED CIRCUIT THAT MITIGATES INDUCTIVE-INDUCED VOLTAGE DROOP USING COMPUTE UNIT GROUP IDENTIFIERS 审中-公开

    公开(公告)号：US20240094794A1

    公开(公告)日：2024-03-21

    申请号：US18132392

    申请日：2023-04-08

    Applicant: SambaNova Systems, Inc.

    Inventor： Darshan GANDHI ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Gregory Frederick GROHOSKI ,  Youngmoon CHOI ,  Jinuk SHIN

    IPC: G06F1/3206 ,  G06F1/08

    CPC classification number: G06F1/3206 ,  G06F1/08

    Abstract: An integrated circuit (IC) includes an array of statically reconfigurable compute units for separation into mutually exclusive groups. Each group includes statically reconfigurable number of compute units. Each compute unit includes a register statically reconfigurable with a group identifier that identifies which group the compute unit belongs to, a counter statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle, and control circuitry that prevents the compute unit from starting to process data until the counter value matches the identifier. According to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

    Delay-Locked Loop with Widened Lock Range
    6.
    发明公开
    Delay-Locked Loop with Widened Lock Range 审中-公开

    公开(公告)号：US20230216512A1

    公开(公告)日：2023-07-06

    申请号：US18090748

    申请日：2022-12-29

    Applicant: SambaNova Systems, Inc.

    Inventor： Fahim UR RAHMAN ,  Jinuk SHIN

    IPC: H03L7/10 ,  H03L7/081 ,  H03L7/093 ,  H03H17/02

    CPC classification number: H03L7/10 ,  H03L7/0812 ,  H03L7/093 ,  H03H17/02 ,  H03H2017/0081

    Abstract: A DLL includes a delay line with two phase outputs, a gater coupled with the delay line phase outputs, a PFD coupled with gater outputs, a PD coupled with PFD outputs, a retimer coupled with PD outputs, and a loop filter with inputs coupled with the retimer and a speed control output coupled with the delay line. The gater passes signals on its two inputs to its two outputs, apart from a first pulse on its first input. The PD determines if the second gated signal leads or lags the first gated signal. The retimer retimes PD output signals to be aligned with a delay line input signal. The loop filter uses the retimed PD output signals to determine if the delay line should delay more or delay less, and outputs a speed control signal to control the delay line speed.

    Timing Margin Sensor
    8.
    发明公开
    Timing Margin Sensor 审中-公开

    公开(公告)号：US20230251683A1

    公开(公告)日：2023-08-10

    申请号：US18104233

    申请日：2023-01-31

    Applicant: SambaNova Systems, Inc.

    Inventor： Mahmood KHAYATZADEH ,  Satyajit SARKAR ,  Jinuk SHIN

    IPC: G06F1/08

    CPC classification number: G06F1/08

    Abstract: A timing margin sensor circuit includes one or more time-to-digital converters (TDCs), a predictor, and a translation circuit. The TDC(s) measure(s) progress of a clock signal through one or more chains of delay stages. The progress depends on sense conditions acting upon the delay chain, such as the supply voltage and the temperature. The predictor receives the measured progress. If the delay chain becomes slower, the predictor extrapolates a predicted progress value. If the delay chain becomes faster, the predictor outputs the actual progress value. The translator translates the predictor output value to sense information that can be used in a clock stretcher circuit. The timing margin sensor may further have an averager/selector to average or select from the results of multiple TDCs. The timing margin sensor may further have a calibrator to compensate for nominal sense conditions, and one or more tunable delays circuits.

    HIGH-BANDWIDTH POWER ESTIMATOR FOR AI ACCELERATOR
    9.
    发明公开
    HIGH-BANDWIDTH POWER ESTIMATOR FOR AI ACCELERATOR 审中-公开

    公开(公告)号：US20230205293A1

    公开(公告)日：2023-06-29

    申请号：US18089891

    申请日：2022-12-28

    Applicant: SambaNova Systems, Inc.

    Inventor： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

    IPC: G06F1/28 ,  G06F9/445

    CPC classification number: G06F1/28 ,  G06F9/44505

    Abstract: A processor IC has multiple power base units (PBUs), arranged in an array. Each PBU includes a switch, a memory unit and a compute unit. It further includes a power estimator for the switch, memory unit, and compute unit. The PBUs communicate with an array-level power accumulator via dedicated wiring. Communication via the dedicated wiring may use timestamps to ensure time-accurate aggregate estimates. The switch power estimator estimates dissipation based on port activity. The memory power estimator estimates dissipation based on read and write activity and bit toggling in the memory. The compute power estimator estimates power based on monitoring input data zero values, bit toggling, instruction type, and activity of reconfigurable processing units. The array-level power accumulator calculates the array-level nominal dynamic power estimate. A power clock management controller scales the dynamic power estimate for the actual clock frequency and measured supply voltage, and adds a static power estimate.

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