公开(公告)号：US20250081729A1

公开(公告)日：2025-03-06

申请号：US18626440

申请日：2024-04-04

Applicant: Samsung Display Co., LTD.

Inventor： Soo Jung CHAE ,  Sung Joon KWAK ,  Jae Hong KIM ,  Tae Sun PARK ,  Jae Hyoung YOUN ,  Je Min LEE

IPC: H10K59/121 ,  H10K59/12 ,  H10K59/131

Abstract: A display device includes a substrate including a display area and a driving circuit area, a first insulating layer, a second insulating layer on the first insulating layer, a first transistor in the display area, and including a first semiconductor pattern layer formed as a semiconductor layer on the second insulating layer, a first gate electrode on the first semiconductor pattern layer, and a first lower electrode overlapping the first semiconductor pattern layer, and a second transistor in the driving circuit area, and including a second semiconductor pattern layer formed as the semiconductor layer, a second gate electrode on the second semiconductor pattern layer, and a second lower electrode overlapping the second semiconductor pattern layer, wherein the first lower electrode is between the substrate and the first insulating layer, and the second lower electrode is between the first insulating layer and the second insulating layer.

公开(公告)号：US20160204135A1

公开(公告)日：2016-07-14

申请号：US14924012

申请日：2015-10-27

Applicant: Samsung Display Co., Ltd.

Inventor： Hyung Min KIM ,  NAM JUNE KIM ,  Jae Hyoung YOUN ,  Jang Soo KIM ,  Se Myung KWON ,  Kang-Young LEE

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1362 ,  H01L27/32

CPC classification number: H01L27/1225 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78696

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate line disposed on a substrate and including a gate electrode; a gate insulating layer formed on the gate line; a first oxide semiconductor layer disposed on the gate insulating layer and formed of an oxide semiconductor; a data wiring layer disposed on the gate insulating layer and including data line intersecting with the gate line, a source electrode connected to the data line, and a drain electrode facing the drain electrode; and a second oxide semiconductor layer covering the source electrode and the drain electrode, wherein the data wiring layer includes copper or a copper alloy.

Abstract translation: 根据本发明的示例性实施例的薄膜晶体管阵列面板包括：栅极线，设置在基板上并包括栅电极; 栅极绝缘层，形成在栅极线上; 设置在所述栅极绝缘层上并由氧化物半导体形成的第一氧化物半导体层; 配置在所述栅极绝缘层上并且包括与所述栅极线交叉的数据线的数据布线层，与所述数据线连接的源电极以及面对所述漏极的漏电极。 以及覆盖源电极和漏电极的第二氧化物半导体层，其中数据布线层包括铜或铜合金。

公开(公告)号：US20230335575A1

公开(公告)日：2023-10-19

申请号：US17975712

申请日：2022-10-28

Applicant: Samsung Display Co., LTD.

Inventor： Jin Woo LEE ,  Cheon Jae MAENG ,  Zu Seok OH ,  Jae Hyoung YOUN ,  Jeong Hyun LEE ,  Seung Jin CHU

IPC: H01L27/15 ,  H01L33/24 ,  H01L33/44 ,  H01L33/50

CPC classification number: H01L27/156 ,  H01L33/24 ,  H01L33/44 ,  H01L33/50 ,  H01L2933/0041

Abstract: A display device including a display area and a non-display area includes: a light emitting element on a base layer in the display area; a dam member on the base layer in the non-display area; a color filter layer disposed in the display area and the non-display area and including an outer color filter layer disposed in the non-display area; and a cover layer on the color filter layer. The cover layer may cover at least a portion of the outer color filter layer.

公开(公告)号：US20200020263A1

公开(公告)日：2020-01-16

申请号：US16292326

申请日：2019-03-05

Applicant: Samsung Display Co., Ltd.

Inventor： Kwan-Yup SHIN ,  Jun-Ho BAE ,  Jae Hyoung YOUN ,  Da Young LEE ,  Jin Young LEE ,  Hyeok Jun LEE

IPC: G09G3/20 ,  G02F1/1345 ,  G02F1/1362 ,  H01L27/32

Abstract: A display device including: a display panel including a plurality of pixels arranged therein; a plurality of gate lines disposed in the display panel to transfer gate signals to the pixels; and a gate driver disposed in the display panel to include a plurality of stages that generate gate signals and output them to the gate lines. A first one of the stages is connected with a first one and a second one of the gate lines through a gate pad, the gate pad includes a first gate pad, a second gate pad, and a third gate pad, and the first gate pad, the second gate pad, and the third gate pad are connected with each other through a gate pad connecting member.