公开(公告)号：US09524990B2

公开(公告)日：2016-12-20

申请号：US14790338

申请日：2015-07-02

Applicant: Samsung Display Co., Ltd.

Inventor： Joong-gun Chong ,  O-Sung Seo ,  Seung-Jun Yu ,  Sang-Myoung Lee ,  Hyoung-Cheol Lee

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1248

Abstract: A display device including: a substrate including first and second sides which face and are parallel to each other, and third and fourth sides which are orthogonal to the first and second sides, and face each other; a gate driver and a data driver disposed along the first side of the substrate; a first diagonal gate line, which is extended in a first direction crossing directions in which the first to fourth sides are extended, and has both ends heading the second and fourth sides of the substrate; a gate pad part extended from one end of the first diagonal gate line adjacent to the second side; an insulation layer including an opening for exposing at least a partial area of the gate pad part and formed on the substrate; a redundancy line extended in a second direction parallel to a direction in which the third and fourth sides are extended, and connected to the gate driver; and a redundancy pad part extended from the redundancy line to be in direct contact with the gate pad part exposed through the opening.

Abstract translation: 一种显示装置，包括：基板，包括彼此面对并且彼此平行的第一和第二侧;以及与所述第一和第二侧正交的第三和第四侧，并且彼此面对; 栅极驱动器和沿着衬底的第一侧布置的数据驱动器; 第一对角线线，其沿着与第一至第四侧延伸的方向交叉的第一方向延伸，并且具有朝向基板的第二和第四侧的两端; 从与所述第二侧相邻的所述第一对角线栅极线的一端延伸的栅极焊盘部分; 绝缘层，包括用于暴露所述栅极焊盘部分的至少一部分区域并形成在所述衬底上的开口; 冗余线在平行于第三和第四侧延伸的方向的第二方向上延伸并连接到栅极驱动器; 以及从冗余线延伸以与通过开口暴露的栅极焊盘部分直接接触的冗余焊盘部分。

公开(公告)号：US08652886B2

公开(公告)日：2014-02-18

申请号：US13870053

申请日：2013-04-25

Applicant: Samsung Display Co., Ltd.

Inventor： Hyeong-Suk Yoo ,  Ho-Jun Lee ,  Sung-Ryul Kim ,  O-Sung Seo ,  Hong-Kee Chin

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1248

Abstract: A method of manufacturing a thin film transistor array substrate includes forming a gate pattern on a substrate, forming a gate insulating film on the substrate, forming a source/drain pattern and a semiconductor pattern on the substrate, forming first, second, and third passivation films successively on the substrate. Over the above multi-layered passivation film forming a first photoresist pattern including a first portion formed on part of the drain electrode and on the pixel region, and a second portion. The second portion is thicker than the first portion. Then, patterning the third passivation film using the first photoresist pattern, forming a second photoresist pattern by removing the first portion of the first photoresist pattern, forming a transparent electrode film on the substrate, removing the second photoresist pattern and the transparent electrode film disposed on the second photoresist pattern, and forming a transparent electrode pattern on the second passivation layer.

Abstract translation: 制造薄膜晶体管阵列基板的方法包括在基板上形成栅极图案，在基板上形成栅极绝缘膜，在基板上形成源/漏图案和半导体图案，形成第一，第二和第三钝化层 胶片依次在基材上。 在上述多层钝化膜上形成包括形成在漏电极的一部分上和在像素区域上的第一部分的第一光致抗蚀剂图案和第二部分。 第二部分比第一部分厚。 然后，使用第一光致抗蚀剂图案图案化第三钝化膜，通过去除第一光致抗蚀剂图案的第一部分形成第二光致抗蚀剂图案，在基板上形成透明电极膜，去除设置在第一光致抗蚀剂图案上的第二光致抗蚀剂图案和透明电极膜 第二光致抗蚀剂图案，并且在第二钝化层上形成透明电极图案。

公开(公告)号：US09443881B2

公开(公告)日：2016-09-13

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jean-Ho Song ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L29/04 ,  H01L27/12 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US20150053984A1

公开(公告)日：2015-02-26

申请号：US14518278

申请日：2014-10-20

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： JEAN-HO SONG ,  Shin-Il Choi ,  Sun-Young Hong ,  Shi-Yul Kim ,  Ki-Yeup Lee ,  Jae-Hyoung Youn ,  Sung-Ryul Kim ,  O-Sung Seo ,  Yang-Ho Bae ,  Jong-Hyun Choung ,  Dong-Ju Yang ,  Bong-Kyun Kim ,  Hwa-Yeul Oh ,  Pil-Soon Hong ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Yu-Gwang Jeong ,  Jong-In Kim ,  Nam-Seok Suh

IPC: H01L27/12 ,  H01L29/45 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/42368 ,  H01L29/458 ,  H01L29/78669

Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.

Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。

公开(公告)号：US20160118410A1

公开(公告)日：2016-04-28

申请号：US14790338

申请日：2015-07-02

Applicant: Samsung Display Co., Ltd.

Inventor： Joong-gun Chong ,  O-Sung Seo ,  Seung-Jun Yu ,  Sang-Myoung Lee ,  Hyoung-Cheol Lee

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/1248

Abstract: A display device including: a substrate including first and second sides which face and are parallel to each other, and third and fourth sides which are orthogonal to the first and second sides, and face each other; a gate driver and a data driver disposed along the first side of the substrate; a first diagonal gate line, which is extended in a first direction crossing directions in which the first to fourth sides are extended, and has both ends heading the second and fourth sides of the substrate; a gate pad part extended from one end of the first diagonal gate line adjacent to the second side; an insulation layer including an opening for exposing at least a partial area of the gate pad part and formed on the substrate; a redundancy line extended in a second direction parallel to a direction in which the third and fourth sides are extended, and connected to the gate driver; and a redundancy pad part extended from the redundancy line to be in direct contact with the gate pad part exposed through the opening.

Abstract translation: 一种显示装置，包括：基板，包括彼此面对并且彼此平行的第一和第二侧;以及与所述第一和第二侧正交的第三和第四侧，并且彼此面对; 栅极驱动器和沿着衬底的第一侧布置的数据驱动器; 第一对角线线，其沿着与第一至第四侧延伸的方向交叉的第一方向延伸，并且具有朝向基板的第二和第四侧的两端; 从与所述第二侧相邻的所述第一对角线栅极线的一端延伸的栅极焊盘部分; 绝缘层，包括用于暴露所述栅极焊盘部分的至少一部分区域并形成在所述衬底上的开口; 冗余线在平行于第三和第四侧延伸的方向的第二方向上延伸并连接到栅极驱动器; 以及从冗余线延伸以与通过开口暴露的栅极焊盘部分直接接触的冗余焊盘部分。