DISPLAY DEVICE
    3.
    发明申请

    公开(公告)号:US20210249542A1

    公开(公告)日:2021-08-12

    申请号:US17086545

    申请日:2020-11-02

    Abstract: A display device including: a first thin film transistor (TFT) including a first semiconductor layer and a first gate electrode, the first semiconductor layer including a first channel region, a first source region, and a first drain region; a third TFT including a third semiconductor layer and a third gate electrode, the third semiconductor layer including a third channel region, a third source region, and a third drain region, wherein a leakage current of the third TFT in an off-state is less than a leakage current of the first TFT in the off-state; and a pixel electrode connected to one of the first source region and the first drain region, wherein the one of the first source region and the first drain region is connected to the third TFT.

    DISPLAY PANEL
    8.
    发明申请
    DISPLAY PANEL 有权
    显示面板

    公开(公告)号:US20150200240A1

    公开(公告)日:2015-07-16

    申请号:US14506061

    申请日:2014-10-03

    CPC classification number: H01L29/7869 H01L29/45 H01L29/66969

    Abstract: A display panel includes a base substrate including a pixel area and a peripheral area, a semiconductor layer disposed on a portion of the base substrate, a display element disposed in the pixel area, and a thin film transistor which controls the display element and includes an input electrode, an output electrode and a control electrode, in which the semiconductor layer includes a first portion disposed on the input electrode of the first thin film transistor, a second portion disposed on the output electrode of the first thin film transistor, and a third portion which connects the first portion and the second portion, overlaps the control electrode of the first thin film transistor, and defines a channel of the first thin film transistor.

    Abstract translation: 显示面板包括:基板,包括像素区域和外围区域;设置在基板的一部分上的半导体层;设置在像素区域中的显示元件;以及控制显示元件的薄膜晶体管, 输入电极,输出电极和控制电极,其中半导体层包括设置在第一薄膜晶体管的输入电极上的第一部分,设置在第一薄膜晶体管的输出电极上的第二部分,以及第三部分 连接第一部分和第二部分的部分与第一薄膜晶体管的控制电极重叠,并限定第一薄膜晶体管的沟道。

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