THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

    公开(公告)号:US20210217760A1

    公开(公告)日:2021-07-15

    申请号:US17021416

    申请日:2020-09-15

    Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEM INCLUDING THE SAME

    公开(公告)号:US20220149072A1

    公开(公告)日:2022-05-12

    申请号:US17375273

    申请日:2021-07-14

    Abstract: A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.

    SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

    公开(公告)号:US20250167115A1

    公开(公告)日:2025-05-22

    申请号:US18925771

    申请日:2024-10-24

    Abstract: A semiconductor device may include a peripheral circuit structure first bonding pads connected to peripheral circuits on a semiconductor substrate; and a cell array structure including second bonding pads bonded to the first bonding pads. The cell array structure may include a separation structure penetrating a stack structure, vertical channel patterns penetrating the stack structure, a source conductive pattern connected to the vertical channel patterns on the stack structure, an upper dielectric layer covering the source conductive pattern, and an upper via that penetrates the upper dielectric layer. The stack structure may include interlayer dielectric layers and conductive patterns that are vertically alternately stacked. The separation structure may include a stop pattern on a dielectric pattern. The source conductive pattern may be in contact with a top surface of the stop pattern. The upper via may connect to the source conductive pattern on the stop pattern.

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