公开(公告)号：US11387817B2

公开(公告)日：2022-07-12

申请号：US17215838

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Gon Kang ,  Woo Kyu Kim ,  Tae Jun Yoo ,  Dal Hee Lee

IPC: H03K3/037 ,  H03K19/20 ,  H03K3/012 ,  H03K3/3562

Abstract: A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.

公开(公告)号：US11996846B2

公开(公告)日：2024-05-28

申请号：US17861939

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoung Gon Kang ,  Woo Kyu Kim ,  Tae Jun Yoo ,  Dal Hee Lee

IPC: H03K3/037 ,  H03K3/012 ,  H03K3/3562 ,  H03K19/20

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/3562 ,  H03K19/20

Abstract: A master latch circuit, including a first p-type transistor, a first n-type transistor, and a second n-type transistor connected in series; a first node connected to the first p-type transistor and the first n-type transistor, and a NAND circuit configured to receive a signal of the first node and a clock signal and output a result of a NAND operation to a second node, wherein a gate of the first p-type transistor is connected to the second node.

公开(公告)号：US20240094987A1

公开(公告)日：2024-03-21

申请号：US18329856

申请日：2023-06-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Gon Kang

IPC: G06F7/501 ,  G06F30/392 ,  H01L27/118 ,  H03K17/00 ,  H03K19/21

CPC classification number: G06F7/501 ,  G06F30/392 ,  H01L27/11807 ,  H03K17/002 ,  H03K19/21 ,  H01L2027/11881 ,  H01L2027/11885

Abstract: A compressor circuit and a semiconductor integrated circuit included the compressor circuit are provided. The semiconductor integrated circuit includes a compressor circuit which includes a first full adder circuit which receives an A1 signal, a B1 signal, and a CI signal to output an IS signal and an ICO signal, and a second full adder circuit which receives a B2 signal, the IS signal, and a CI2 signal to output an S signal and a CO signal. Each of the first full adder circuit and the second full adder circuit are in an L-shaped layout, the first full adder circuit and the second full adder circuit have bent portions that are point-symmetrically engaged with each other, and the compressor circuit is in a rectangular shape. The number of transistors in the second full adder circuit is smaller than the number of transistors in the first full adder circuit.

公开(公告)号：US12078679B2

公开(公告)日：2024-09-03

申请号：US18338237

申请日：2023-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Gon Kang

IPC: H03K19/20 ,  G01R31/3185 ,  G11C7/10 ,  G11C7/22 ,  H03K3/037

CPC classification number: G01R31/318541 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/222 ,  H03K3/0372 ,  H03K19/20

Abstract: A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.

公开(公告)号：US11726141B2

公开(公告)日：2023-08-15

申请号：US17720242

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Gon Kang

IPC: H03K3/03 ,  G01R31/3185 ,  G11C7/22 ,  H03K19/20 ,  G11C7/10 ,  H03K3/037

CPC classification number: G01R31/318541 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/222 ,  H03K3/0372 ,  H03K19/20

Abstract: A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.

公开(公告)号：US20230333162A1

公开(公告)日：2023-10-19

申请号：US18338237

申请日：2023-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Gon Kang

IPC: G01R31/3185 ,  G11C7/22 ,  G11C7/10 ,  H03K19/20 ,  H03K3/037

CPC classification number: G01R31/318541 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/222 ,  H03K3/0372 ,  H03K19/20

Abstract: A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.

公开(公告)号：US20220397607A1

公开(公告)日：2022-12-15

申请号：US17720242

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung Gon Kang

IPC: G01R31/3185 ,  G11C7/22 ,  G11C7/10 ,  H03K3/037 ,  H03K19/20

Abstract: A flip-flop circuit includes a clock generator configured to generate first and second clock signals having different phases relative to each other, and a master-slave latch circuit including master and slave latches. The master latch includes a scan path configured to output a scan path signal in response to a scan enable signal and a scan input signal, and a data path configured to output a first latch signal in response to a data signal and the scan path signal. A feedback path is provided, which includes a tri-state inverter responsive to the first and second clock signals. The tri-state inverter has an input terminal connected to an output terminal of the data path and an output terminal connected to a node of the scan path.