公开(公告)号：US11372551B2

公开(公告)日：2022-06-28

申请号：US16898935

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byungyong Choi ,  Doohyun Kim ,  Changkyu Seol ,  Ilhan Park

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: A method of operating a memory controller, the method including performing a state shaping operation on received data based on state shaping information in response to a write request, the received data and the write request being received from a host, the state shaping information representing a memory cell characteristic corresponding to a memory cell group on which the received data is to be programmed, and the state shaping information being received from a memory device, and transmitting transformation data to the memory device, the transformation data being generated through the state shaping operation.

公开(公告)号：US11171152B2

公开(公告)日：2021-11-09

申请号：US16588067

申请日：2019-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chunghwan Yang ,  Joyoung Park ,  Taeyun Bae ,  Byungyong Choi

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A three-dimensional flash memory device is described that may include a substrate, a plurality of cell gate patterns and a plurality of mold insulating layers alternately stacked on the substrate, and a vertical channel structure in contact with side surfaces of the plurality of cell gate patterns and side surfaces of the plurality of mold insulating layers. Each of the plurality of cell gate patterns may include a cell gate electrode and a blocking barrier pattern adjacently disposed on one side surface of the cell gate electrode. An inner side surface of the blocking barrier pattern may include an upper inner side surface, a middle inner side surface, and a lower inner side surface. The middle inner side surface of the blocking barrier pattern may face the one side surface of the cell gate electrode. The blocking barrier pattern may have a portion protruding toward the cell gate electrode at a connection point between the upper inner side surface of the blocking barrier pattern and the middle inner side surface of the blocking barrier pattern.

公开(公告)号：US20220130849A1

公开(公告)日：2022-04-28

申请号：US17350760

申请日：2021-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyukje Kwon ,  Byungyong Choi ,  Jisang Lee

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A memory device includes a cell region in which memory blocks, respectively including gate electrodes and insulating layers, alternately stacked on a substrate, and channel structures, extending in a first direction, perpendicular to an upper surface of the substrate, passing through the gate electrodes and the insulating layers, and connected to the substrate, are arranged. A peripheral circuit region includes a row decoder connected to the gate electrodes and a page buffer connected to the channel structures. The memory blocks include main blocks and at least one spare block, wherein a length of the spare block is shorter than a length of each of the main blocks, in a second direction, parallel to the upper surface of the substrate.

公开(公告)号：US10903236B2

公开(公告)日：2021-01-26

申请号：US16663228

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kangyoon Choi ,  Dong-Sik Lee ,  Jongwon Kim ,  Gilsung Lee ,  Eunsuk Cho ,  Byungyong Choi ,  Sung-Min Hwang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/04 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/02

Abstract: A three-dimensional (3D) semiconductor memory device includes a substrate that includes a cell array region and a connection region, a dummy trench formed on the connection region, an electrode structure on the substrate and that includes vertically stacked electrodes that have a staircase structure on the connection region, a dummy insulating structure disposed in the dummy trench, the dummy insulating structure including an etch stop pattern spaced apart from the substrate and the electrode structure, a cell channel structure disposed on the cell array region and that penetrates the electrode structure and makes contact with the substrate, and a dummy channel structure disposed on the connection region and that penetrates the electrode structure and a portion of the dummy insulating structure and that makes contact with the etch stop pattern.