公开(公告)号：US10553438B2

公开(公告)日：2020-02-04

申请号：US15409813

申请日：2017-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yun Kyeong Jang ,  Sang Jin Kim ,  Dong Woon Park ,  Joon Soo Park ,  Chang Jae Yang ,  Kwang Sub Yoon ,  Hye Kyoung Jue

IPC: H01L21/28 ,  H01L21/033 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device includes stacking a semiconductor layer, a first sacrificial layer, and a second sacrificial layer, patterning the second sacrificial layer to form a second sacrificial pattern, forming a spacer pattern on both sides of the second sacrificial pattern, wherein a pitch of the spacer pattern is constant, and a width of the spacer pattern is constant, removing the second sacrificial pattern, forming a mask layer that covers the spacer pattern, forming a supporting pattern on the mask layer, wherein a width of the supporting pattern is greater than a width of the spacer pattern, and the supporting pattern is overlapped with the spacer pattern, transferring the supporting pattern and the spacer pattern onto the first sacrificial layer to form gate and supporting patterns, and transferring the gate and supporting patterns onto the semiconductor layer to form a gate and a supporting gate.

公开(公告)号：US09576955B2

公开(公告)日：2017-02-21

申请号：US14992683

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hwan Lee ,  Tae Yong Kwon ,  Sang Su Kim ,  Chang Jae Yang ,  Jung Han Lee ,  Hwan Wook Choi ,  Yeon Cheol Heo ,  Sang Hyuk Hong

IPC: H01L21/84 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Abstract translation: 提供半导体器件。 半导体器件包括活性鳍片，其包括设置在衬底上的缓冲层和设置在缓冲层上并具有高于缓冲层的晶格常数的第一晶格常数的沟道层，栅极结构覆盖沟道层并与 设置在栅极结构的两个侧壁上的活动翅片，侧壁间隔物以及设置成接触侧壁间隔物的下表面并具有与侧壁间隔物的下表面的宽度基本相同的宽度的封盖层。