公开(公告)号：US11670636B2

公开(公告)日：2023-06-06

申请号：US17577549

申请日：2022-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Yong Kwon ,  Byoung-Gi Kim ,  Ki Hwan Lee ,  Jung Han Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6681 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

公开(公告)号：US10892347B2

公开(公告)日：2021-01-12

申请号：US16197752

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L29/739

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US10164057B1

公开(公告)日：2018-12-25

申请号：US15878711

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub Jeon ,  Tae Yong Kwon ,  Oh Seong Kwon ,  Soo Yeon Jeong ,  Yong Hee Park ,  Jong Ryeol Yoo

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US20180315667A1

公开(公告)日：2018-11-01

申请号：US15854343

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Yong Kwon ,  Oh Seong Kwon

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L21/027 ,  H01L21/311 ,  H01L29/49

Abstract: A method of fabricating a gate all around semiconductor device is provided. The method includes: providing a semiconductor substrate having a plurality of active fins extending in a first direction in a first region and a second region next to the first region, a plurality of gate all around channels stacked above each of the plurality of active fins, and a plurality of gate openings extending in a second direction across the first and second regions and crossing the plurality of active fins, in which the plurality of gate openings include cave-like gate spaces between each of the plurality of active fins and one adjacent gate all around channel and between two adjacent gate all around channels, forming a dielectric layer in the first and second regions on bottom and sidewalls of each of the plurality of gate openings, and on and surrounding each of the plurality of gate all around channels and filling a first portion of each of the cave-like gate spaces, forming first work function metal in the first and second regions on the dielectric layer with the first work function metal filling a second portion of each of the cave-like gate spaces, forming first carbon-based mask in the first and second regions by a chemical vapor deposition (CVD) process to fill the plurality of gate openings to a height at least covering all the plurality of gate all around channels, forming second carbon-based mask in the first and second regions on top of the first carbon-based mask to a height above the plurality of gate openings, removing the first and second carbon-based masks in the second region, removing the first work function metal in the second region through etching using remaining first and second carbon-based masks in the first region as an etching mask, removing the remaining first and second carbon-based masks in the first region, and forming second work function metal on the dielectric layer in the second region, and on the first work function metal in the first region.

公开(公告)号：US09576955B2

公开(公告)日：2017-02-21

申请号：US14992683

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hwan Lee ,  Tae Yong Kwon ,  Sang Su Kim ,  Chang Jae Yang ,  Jung Han Lee ,  Hwan Wook Choi ,  Yeon Cheol Heo ,  Sang Hyuk Hong

IPC: H01L21/84 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Abstract translation: 提供半导体器件。 半导体器件包括活性鳍片，其包括设置在衬底上的缓冲层和设置在缓冲层上并具有高于缓冲层的晶格常数的第一晶格常数的沟道层，栅极结构覆盖沟道层并与 设置在栅极结构的两个侧壁上的活动翅片，侧壁间隔物以及设置成接触侧壁间隔物的下表面并具有与侧壁间隔物的下表面的宽度基本相同的宽度的封盖层。

公开(公告)号：US11282835B2

公开(公告)日：2022-03-22

申请号：US16735984

申请日：2020-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Yong Kwon ,  Byoung-Gi Kim ,  Ki Hwan Lee ,  Jung Han Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a substrate having first and second regions, first fin groups spaced along a first direction on the first region, each of the first fin groups including adjacent first and second fins having longitudinal directions in a second direction intersecting the first direction, and third to fifth fins spaced along a third direction on the second region, the third to fifth fins having longitudinal directions in a fourth direction intersecting the third direction. The third through fifth fins are at a first pitch, the first and second fins are at a second pitch equal to or smaller than the first pitch, each of the first fin groups is at a first group pitch greater than three times the first pitch and smaller than four times the first pitch, and a width of the first and second fins is same as width of the third fin.

公开(公告)号：US10804391B2

公开(公告)日：2020-10-13

申请号：US16286023

申请日：2019-02-26

Applicant: Samsung Electronics Co., Ltd. ,  International Business Machines Corporation

Inventor： Tae Yong Kwon ,  Kang Ill Seo ,  Oh Seong Kwon ,  Ki Sik Choi

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a channel region that protrudes from an upper surface of a substrate in a vertical direction, forming a gate insulator layer on a side of the channel region, after forming the gate insulator layer, forming a top source/drain on the channel region, and forming a gate electrode on the gate insulator layer.

公开(公告)号：US10566245B2

公开(公告)日：2020-02-18

申请号：US15854343

申请日：2017-12-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae Yong Kwon ,  Oh Seong Kwon

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L21/027 ,  H01L21/311 ,  H01L29/423

Abstract: A method of fabricating a gate all around semiconductor device is provided. The method includes: providing a semiconductor substrate having a plurality of active fins extending in a first direction in a first region and a second region next to the first region, a plurality of gate all around channels stacked above each of the plurality of active fins, and a plurality of gate openings extending in a second direction across the first and second regions and crossing the plurality of active fins, in which the plurality of gate openings include cave-like gate spaces between each of the plurality of active fins and one adjacent gate all around channel and between two adjacent gate all around channels, forming a dielectric layer in the first and second regions on bottom and sidewalls of each of the plurality of gate openings, and on and surrounding each of the plurality of gate all around channels and filling a first portion of each of the cave-like gate spaces, forming first work function metal in the first and second regions on the dielectric layer with the first work function metal filling a second portion of each of the cave-like gate spaces, forming first carbon-based mask in the first and second regions by a chemical vapor deposition (CVD) process to fill the plurality of gate openings to a height at least covering all the plurality of gate all around channels, forming second carbon-based mask in the first and second regions on top of the first carbon-based mask to a height above the plurality of gate openings, removing the first and second carbon-based masks in the second region, removing the first work function metal in the second region through etching using remaining first and second carbon-based masks in the first region as an etching mask, removing the remaining first and second carbon-based masks in the first region, and forming second work function metal on the dielectric layer in the second region, and on the first work function metal in the first region.