公开(公告)号：US10276564B2

公开(公告)日：2019-04-30

申请号：US15489093

申请日：2017-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mirco Cantoro ,  Yeon Cheol Heo ,  Byoung Gi Kim ,  Chang Min Yoe ,  Seung Chan Yun ,  Dong Hun Lee ,  Yun Il Lee ,  Hyung Suk Lee

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L23/50 ,  H01L21/8234 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/40 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate having a first region and a second region; a first nanowire in the first region in a direction perpendicular to an upper surface of the substrate; a second nanowire in the second region in a direction perpendicular to the upper surface of the substrate and having a height less than that of the first nanowire; first source/drain regions at top portion and bottom portion of the first nanowire; second source/drain regions at top portion and bottom portion of the second nanowire; a first gate electrode surrounding the first nanowire between the first source/drain regions; and a second gate electrode surrounding the second nanowire between the second source/drain regions.

公开(公告)号：US09576955B2

公开(公告)日：2017-02-21

申请号：US14992683

申请日：2016-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hwan Lee ,  Tae Yong Kwon ,  Sang Su Kim ,  Chang Jae Yang ,  Jung Han Lee ,  Hwan Wook Choi ,  Yeon Cheol Heo ,  Sang Hyuk Hong

IPC: H01L21/84 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/7849

Abstract: Semiconductor devices are provided. The semiconductor devices include active fins including a buffer layer disposed on a substrate and a channel layer disposed on the buffer layer and having a first second lattice constant higher than a lattice constant of the buffer layer, a gate structure covering the channel layer and intersecting the active fins, sidewall spacers disposed on both sidewalls of the gate structure, and capping layers disposed to contact lower surfaces of the sidewall spacers and having a width substantially the same as a width of the lower surfaces of the sidewall spacers.

Abstract translation: 提供半导体器件。 半导体器件包括活性鳍片，其包括设置在衬底上的缓冲层和设置在缓冲层上并具有高于缓冲层的晶格常数的第一晶格常数的沟道层，栅极结构覆盖沟道层并与 设置在栅极结构的两个侧壁上的活动翅片，侧壁间隔物以及设置成接触侧壁间隔物的下表面并具有与侧壁间隔物的下表面的宽度基本相同的宽度的封盖层。