公开(公告)号：US20130254386A1

公开(公告)日：2013-09-26

申请号：US13848622

申请日：2013-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ho Kim ,  Sun-Mi Kim ,  Won Woo Ro ,  Changmin Lee ,  Wonseb Jeong ,  Jin-Won Kim

IPC: G06F15/173

CPC classification number: G06F15/173 ,  H04L67/322 ,  H04L69/24

Abstract: According to one embodiment, a scheduling method for load balancing in an electronic device such as a server when performing multiple transcoding operations includes performing a first transcoding operation in order to transmit at least one moving image file to a first terminal. The server receives a request from a second terminal to transmit at least one moving image file while performing the first transcoding. The server performs a second transcoding operation in order to transmit the requested moving image file to the second terminal. The server monitors output frame rates of the first transcoding operation and the second transcoding operation, to control the output frame rates.

Abstract translation: 根据一个实施例，当执行多个代码转换操作时，诸如服务器之类的电子设备中的负载平衡的调度方法包括执行第一代码转换操作，以将至少一个运动图像文件发送到第一终端。 服务器在执行第一代码转换时接收来自第二终端的请求以发送至少一个运动图像文件。 服务器执行第二代码转换操作，以便将请求的运动图像文件发送到第二终端。 服务器监视第一代码转换操作和第二代码转换操作的输出帧速率，以控制输出帧速率。

公开(公告)号：US11610624B2

公开(公告)日：2023-03-21

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

公开(公告)号：US20220215871A1

公开(公告)日：2022-07-07

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4096

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11670355B2

公开(公告)日：2023-06-06

申请号：US17406511

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Namhyung Kim ,  Daejeong Kim ,  Dohan Kim ,  Chanik Park ,  Deokho Seo ,  Wonjae Shin ,  Changmin Lee ,  Ilguy Jung ,  Insu Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/40615 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/40618

Abstract: Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20200174882A1

公开(公告)日：2020-06-04

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C29/52 ,  G11C11/00 ,  G11C11/406

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US11995798B2

公开(公告)日：2024-05-28

申请号：US17439146

申请日：2021-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joohyung Lee ,  Byounggeun Choi ,  Changhoon Kang ,  Junsang You ,  Changmin Lee ,  Younghun Joo ,  Jaeho Choi ,  Hyoungho Choi

IPC: G06T5/00 ,  G06F21/60 ,  G06T5/50

CPC classification number: G06T5/00 ,  G06F21/602 ,  G06T5/50 ,  G06F2221/2141 ,  G06T2207/20224

Abstract: A method and a device are provided. The device includes a camera module, a communication module, a memory, and a processor operatively coupled to the camera module, the communication module, and the memory, wherein the processor is configured to acquire a first content through the camera module or the communication module, generate a second content by editing the first content, based on a user input, store the acquired first content in a secure area of the memory, and store the second content including metadata corresponding to the second content and first content access information corresponding to the first content in a general area of the memory, and the first content access information associates the first content with the second content.

公开(公告)号：US10922170B2

公开(公告)日：2021-02-16

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/00 ,  G11C29/52

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US10884655B2

公开(公告)日：2021-01-05

申请号：US16386645

申请日：2019-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Do-Han Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Kwanghee Lee ,  Changmin Lee ,  Insu Choi

IPC: G06F3/06 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/02

Abstract: A storage module includes a dynamic random access memory (DRAM) device, a nonvolatile memory device, and a high-speed buffer memory. An method of operating the storage module includes copying target data stored in the nonvolatile memory device to the high-speed buffer memory in response to an external device entering a page fault mode, receiving a first refresh command from the external device, and, in response to the first refresh command, performing a first refresh operation associated with the DRAM device and moving the target data copied to the high-speed buffer memory to the DRAM device during a first refresh reference time.

公开(公告)号：US11487613B2

公开(公告)日：2022-11-01

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Minsu Kim ,  Deokho Seo ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/30

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.