公开(公告)号：US11157342B2

公开(公告)日：2021-10-26

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong Ko ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Yongjun Yu ,  Insu Choi ,  Hui-Chung Byun ,  JongYoung Lee

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US11474717B2

公开(公告)日：2022-10-18

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10852969B2

公开(公告)日：2020-12-01

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US11487613B2

公开(公告)日：2022-11-01

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Minsu Kim ,  Deokho Seo ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/30

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

公开(公告)号：US20190310784A1

公开(公告)日：2019-10-10

申请号：US16205357

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F3/06

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.

公开(公告)号：US20190310783A1

公开(公告)日：2019-10-10

申请号：US16363034

申请日：2019-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US11210208B2

公开(公告)日：2021-12-28

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Jiseok Kang ,  Tae-Kyeong Ko ,  Sung-Joon Kim ,  Wooseop Kim ,  Chanik Park ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F12/02 ,  G11C11/56 ,  G06F3/06 ,  G06F13/16

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

公开(公告)号：US10922170B2

公开(公告)日：2021-02-16

申请号：US16412468

申请日：2019-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/406 ,  G11C11/00 ,  G11C29/52

Abstract: A memory system includes a memory device having a plurality of volatile memory modules therein, and a memory controller, which is electrically coupled to the plurality of volatile memory modules. The memory controller is configured to correct an error in a first of the plurality of volatile memory modules in response to generation of an alert signal by the first of the plurality of volatile memory modules, concurrently with an operation to refresh at least a portion of a second of the plurality of volatile memory modules upon the generation of the alert signal.

公开(公告)号：US20210042046A1

公开(公告)日：2021-02-11

申请号：US17082448

申请日：2020-10-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjun Yu ,  Insu Choi ,  Dae-Jeong Kim ,  Sung-Joon Kim ,  Wonjae Shin

IPC: G06F3/06 ,  G06F12/0802

Abstract: Memory systems include a first semiconductor memory module and a processor. The processor is configured to access the first semiconductor memory module by units of a page, and further configured to respond to an occurrence of a page fault in a specific page, which is associated with a virtual address corresponding to an access target, by adjusting a number of pages and allocating pages in the first semiconductor memory module corresponding to the adjusted number of the pages, which are associated with the virtual address.

公开(公告)号：US10740010B2

公开(公告)日：2020-08-11

申请号：US16205357

申请日：2018-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Joon Kim ,  Dae-Jeong Kim ,  Wonjae Shin ,  Yongjun Yu ,  Insu Choi

IPC: G06F3/06

Abstract: A memory module includes a first type memory, a second type memory, a serial presence detect device and a controller. The serial presence detect device is configured to transfer capacity information of the second type memory to an external host device, during an initialization operation. The controller is configured to transfer a training command for the second type memory received from the external host device to the first type memory, during a training operation, which follows in time the initialization operation.