公开(公告)号：US12236104B2

公开(公告)日：2025-02-25

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong Kim ,  Tae-Kyeong Ko ,  Nam Hyung Kim ,  Do-Han Kim ,  Deokho Seo ,  Ho-Young Lee ,  Insu Choi

IPC: G06F11/00 ,  G06F3/06 ,  G06F11/07

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

公开(公告)号：US09934830B2

公开(公告)日：2018-04-03

申请号：US15298335

申请日：2016-10-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongmin Park ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Sungup Moon ,  Kyoyeon Won

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/02

CPC classification number: G11C7/1012 ,  G11C7/02 ,  G11C7/22

Abstract: In a memory module including a memory device and a filter, the memory device operates with a clock of a reference frequency. The filter receives a multiplexed signal from a host and filters a signal of a frequency band from the multiplexed signal. The frequency band includes the reference frequency and the signal of the frequency band is provided to the memory device.

公开(公告)号：US11887692B2

公开(公告)日：2024-01-30

申请号：US17535861

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Insu Choi

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18

CPC classification number: G11C7/222 ,  G11C7/1009 ,  G11C7/109 ,  G11C7/1063 ,  G11C8/18

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

公开(公告)号：US11321177B2

公开(公告)日：2022-05-03

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Deokho Seo ,  Wonjae Shin ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G06F11/10 ,  G11C11/4091 ,  G11C11/408

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US11023396B2

公开(公告)日：2021-06-01

申请号：US16519487

申请日：2019-07-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

公开(公告)号：US20240339145A1

公开(公告)日：2024-10-10

申请号：US18422770

申请日：2024-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongha Kim ,  Tae-Kyeong Ko ,  Do-Han Kim

IPC: G11C11/406 ,  G11C11/4078

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4078

Abstract: The present disclosure relates to operation methods of a memory device including multiple rows each including multiple memory cells. One example method includes receiving an active command for a first row from a memory controller, reading a first count from a per-row hammer tracking (PRHT) region of the first row, updating the first count to generate a first updated count, comparing the first updated count with one of first and second thresholds to generate a comparison result, wherein when the first row is adjacent to the given row, the first updated count is compared with the first threshold and when the first row is not adjacent to the given row, the first updated count is compared with the second threshold, outputting a target row address based on the comparison result, and performing a row hammer mitigation operation on a row corresponding to the target row address.

公开(公告)号：US11631443B2

公开(公告)日：2023-04-18

申请号：US17480359

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jun Yu ,  Nam Hyung Kim ,  Do-Han Kim ,  Min Su Kim ,  Deok Ho Seo ,  Won Jae Shin ,  Chang Min Lee ,  Il Gyu Jung ,  In Su Choi

IPC: G11C7/10 ,  G11C7/22

Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.

公开(公告)号：US11531585B2

公开(公告)日：2022-12-20

申请号：US17177415

申请日：2021-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok Ho Seo ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Min Su Kim ,  Won Jae Shin ,  Yong Jun Yu ,  Chang Min Lee ,  Il Gyu Jung ,  In Su Choi

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52 ,  G11C11/406 ,  G11C29/10

Abstract: A memory module includes a memory device configured to receive a first refresh command from a host, and perform a refresh operation in response to the first refresh command during a refresh time, and a computing unit configured to detect the first refresh command provided from the host to the memory device, and write a first error pattern at a first address of the memory device during the refresh time.

公开(公告)号：US10366021B2

公开(公告)日：2019-07-30

申请号：US15390063

申请日：2016-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungup Moon ,  Tae-Kyeong Ko ,  Do-Han Kim ,  Jongmin Park ,  Kyoyeon Won

IPC: G06F13/16 ,  G06F12/08 ,  G06F12/0804 ,  G06F13/40 ,  G06F12/0868

Abstract: A memory system includes a nonvolatile memory electrically connected to a data bus, a DRAM electrically connected to the data bus, and a memory controller configured to drive the DRAM as a cache memory and the nonvolatile memory as a main memory and to synchronize data of a cache line with data of the nonvolatile memory in units of cache units based on a dirty flag. The DRAM is configured to load data of the cache line that caches data stored in the nonvolatile memory and to store the dirty flag, which indicates whether a cache unit is dirty, in units of cache units, where a size of each cache unit is smaller than a size of the cache line.

公开(公告)号：US11487613B2

公开(公告)日：2022-11-01

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Minsu Kim ,  Deokho Seo ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/30

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.