公开(公告)号：US09190272B1

公开(公告)日：2015-11-17

申请号：US14331715

申请日：2014-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： CheolWoo Park ,  Kwangyul Lee ,  Jeongeon Lee ,  Seokjun Won ,  HyungSuk Jung

IPC: H01L21/033 ,  H01L29/51 ,  H01L27/088 ,  H01L29/49 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L21/02063 ,  H01L21/28114 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66575

Abstract: Provided is a semiconductor device and method of fabricating the same. The device includes a substrate including a first region and a second region, a first gate pattern on the first region, a second gate pattern on the second region, and an interlayer insulating layer enclosing the first and second gate patterns. The first gate pattern including a first gate insulating layer and a first gate electrode, the second gate pattern including a second gate insulating layer and a second gate electrode, the first gate insulating layer is thicker than the second gate insulating layer, and a top width of the second gate pattern is larger than a bottom width thereof.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括：衬底，包括第一区域和第二区域，第一区域上的第一栅极图案，第二区域上的第二栅极图案，以及包围第一和第二栅极图案的层间绝缘层。 第一栅极图案包括第一栅极绝缘层和第一栅极电极，第二栅极图案包括第二栅极绝缘层和第二栅极电极，第一栅极绝缘层比第二栅极绝缘层厚，顶部宽度 的第二栅极图案大于其底部宽度。