公开(公告)号：US20160293728A1

公开(公告)日：2016-10-06

申请号：US15080706

申请日：2016-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Woo SEO ,  Sang-Jin KIM ,  Jong-Seo HONG ,  Jong-Hoon NAH ,  Choon-Ho SONG

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/033

CPC classification number: G03F7/2022 ,  G03F7/2002 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.

Abstract translation: 公开了半导体器件的制造方法。 在由衬底的边缘区域限定的图案区域上形成虚拟栅极结构。 形成层间绝缘层图案以覆盖图案区域并暴露衬底的边缘区域。 在层间绝缘层图案上形成阻挡图案，使得衬底的边缘区域被阻挡图案覆盖，并且通过阻挡图案露出衬底的图案区域。 对应于虚拟栅极结构的衬底的图案区域中的栅极孔，并且在栅极孔中形成金属栅极结构。 因此，衬底的边缘区域在蚀刻工艺和替换栅极金属（RGM）工艺的沉积工艺中被保护。