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    METHODS OF FORMING HOLE PATTERNS OF SEMICONDUCTOR DEVICES
    1.
    发明申请
    METHODS OF FORMING HOLE PATTERNS OF SEMICONDUCTOR DEVICES 有权
    形成半导体器件孔洞图案的方法

    公开(公告)号：US20140220782A1

    公开(公告)日：2014-08-07

    申请号：US14043361

    申请日：2013-10-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Woo SEO

    IPC: H01L21/308

    CPC classification number: H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/32139

    Abstract: A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern.

    Abstract translation: 使用蚀刻选择性形成具有小间距的多个孔图案的双重图案化方法包括形成限定暴露缓冲掩模层的上表面的预备孔的图案化掩模图案，暴露缓冲掩模层的上表面的内部间隔 在预备孔的内壁上，具有第一孔的缓冲掩模图案和填充预备孔和第一孔的芯绝缘图案，将外部间隔物露出在图案形成掩模图案的暴露部分的第一部分上 内部间隔物的外侧，以及露出缓冲掩模图案的第一部分的空白空间。 图案化掩模图案的第二部分和缓冲掩模图案的第二部分被暴露。 通过去除缓冲掩模图案的第二部分来形成第二孔。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES
    3.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES 有权
    制造半导体器件的方法

    公开(公告)号：US20160293728A1

    公开(公告)日：2016-10-06

    申请号：US15080706

    申请日：2016-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jung-Woo SEO ,  Sang-Jin KIM ,  Jong-Seo HONG ,  Jong-Hoon NAH ,  Choon-Ho SONG

    IPC: H01L29/66 ,  H01L21/311 ,  H01L21/033

    CPC classification number: G03F7/2022 ,  G03F7/2002 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/66795

    Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.

    Abstract translation: 公开了半导体器件的制造方法。 在由衬底的边缘区域限定的图案区域上形成虚拟栅极结构。 形成层间绝缘层图案以覆盖图案区域并暴露衬底的边缘区域。 在层间绝缘层图案上形成阻挡图案，使得衬底的边缘区域被阻挡图案覆盖，并且通过阻挡图案露出衬底的图案区域。 对应于虚拟栅极结构的衬底的图案区域中的栅极孔，并且在栅极孔中形成金属栅极结构。 因此，衬底的边缘区域在蚀刻工艺和替换栅极金属（RGM）工艺的沉积工艺中被保护。

    SEMICONDUCTOR DEVICES
    4.
    发明申请
    SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20200176455A1

    公开(公告)日：2020-06-04

    申请号：US16782213

    申请日：2020-02-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun-Kyum KIM ,  Jung-Woo SEO ,  Sung-Un KWON

    IPC: H01L27/108 ,  H01L21/768

    Abstract: A semiconductor device can include a plurality of landing pads arranged according to a layout on a substrate, wherein a cross-sectional shape of each of the landing pads has a diamond shape so that opposing interior angles of the diamond shape are equal to one another and adjacent interior angles of the diamond shape are unequal to one another.

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