公开(公告)号：US20190148292A1

公开(公告)日：2019-05-16

申请号：US16244137

申请日：2019-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung Sung Kim ,  Hyeon Uk Kim ,  Young Gook Park ,  Chul Hong Park

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.

公开(公告)号：US10217705B1

公开(公告)日：2019-02-26

申请号：US15894968

申请日：2018-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung Sung Kim ,  Hyeon Uk Kim ,  Young Gook Park ,  Chul Hong Park

IPC: H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.

公开(公告)号：US10546855B2

公开(公告)日：2020-01-28

申请号：US15473913

申请日：2017-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rajeev Ranjan ,  Deepak Sharma ,  Subhash Kuchanuri ,  Chul Hong Park ,  Jae Seok Yang ,  Kwan Young Chun

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522

Abstract: Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.

公开(公告)号：US20230361036A1

公开(公告)日：2023-11-09

申请号：US18140356

申请日：2023-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung Ju KANG ,  Kwan Young Chun ,  Ji Wook Kwon ,  Chul Hong Park ,  Azmat Raheel ,  Suhyeong Choi

IPC: H01L23/528 ,  H01L23/48

CPC classification number: H01L23/5286 ,  H01L23/481

Abstract: A semiconductor device includes a substrate including a first side and a second side opposite to the first side, a first power rail and a second power rail provided on the first side of the substrate, the first power rail and the second power rail extending in a first direction and being separated in a second direction, a first active region and a second active region provided on the first side of the substrate, the first active region and the second active region being defined by an element separation film between the first power rail and the second power rail and being separated in the second direction, a power delivery network provided on the second side of the substrate, and a first power through via penetrating the element separation film and the substrate, the first power through via connecting the power delivery network and the first power rail.

公开(公告)号：US10923420B2

公开(公告)日：2021-02-16

申请号：US15873352

申请日：2018-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Wook Oh ,  Dong Hyun Kim ,  Doo Hwan Park ,  Sung Keun Park ,  Chul Hong Park ,  Sung Wook Hwang

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L23/532 ,  H01L21/285

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

公开(公告)号：US20230361037A1

公开(公告)日：2023-11-09

申请号：US18304560

申请日：2023-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung Ju Kang ,  Pan Jae Park ,  Ji Wook Kwon ,  Chul Hong Park ,  Jae Seok Yang

IPC: H01L23/528 ,  H01L27/092 ,  H01L23/48 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  G06F30/31

CPC classification number: H01L23/5286 ,  H01L27/092 ,  H01L23/481 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  G06F30/31

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a first side and a second side that are opposite to each other, a power tap cell in a first row, a second row adjacent to the first row, and a third row adjacent to the second row, on the first side of the substrate, a first power rail and a second power rail on the power tap cell, that extend in a first direction and are spaced apart from each other in a second direction, and a power delivery network on the second side of the substrate. The power tap cell includes a first power through via that penetrates the substrate and extends from the power delivery network to the first power rail, and a second power through via that penetrates the substrate and extends from the power delivery network to the second power rail.

公开(公告)号：US20190043804A1

公开(公告)日：2019-02-07

申请号：US15894968

申请日：2018-02-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yubo Qian ,  Byung Sung Kim ,  Hyeon Uk Kim ,  Young Gook Park ,  Chul Hong Park

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device includes a first conductive element, a first insulating layer and a second insulating layer sequentially disposed on the first conductive element, a conductive via passing through the first insulating layer and the second insulating layer. The conductive via is connected to the first conductive element. The semiconductor device includes a via extension portion disposed in the second insulating layer that extends along an upper surface of the first insulating layer from one side surface of the conductive via, and a second conductive element disposed on the second insulating layer that is connected to the via extension portion.

公开(公告)号：US10185798B2

公开(公告)日：2019-01-22

申请号：US15343860

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin Kim ,  Su Hyeon Kim ,  Azmat Raheel ,  Chul Hong Park

IPC: G06F17/50 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided. The fabricating method of a semiconductor device includes loading a first layout, wherein the first layout comprises a first active region and a first dummy region, and the first active region comprises a fin-type pattern design having a first width, generating a second layout by substituting the fin-type pattern design with a nanowire structure design and forming a nanowire structure by using the second layout, wherein the second layout comprises a second active region in the same size as the first active region, and a second dummy region in the same size as the first dummy region, the nanowire structure design has a second width greater than the first width, and the nanowire structure comprises a first nanowire extending in a first direction, a second nanowire extending in the first direction and being formed on the first nanowire at a spacing apart from the first nanowire, a gate electrode surrounding a periphery of the first nanowire and extending in a second direction of intersecting with the first direction, a gate spacer being formed on a sidewall of the gate electrode and comprising an inner sidewall and an outer sidewall facing each other, the inner sidewall of the gate spacer facing a side surface of the gate electrode, and a source/drain epitaxial layer on at least one side of the gate electrode and being connected to the first nanowire.