Method of Forming a Step Pattern Structure
    1.
    发明申请
    Method of Forming a Step Pattern Structure 有权
    形成步骤图案结构的方法

    公开(公告)号:US20140057429A1

    公开(公告)日:2014-02-27

    申请号:US13910734

    申请日:2013-06-05

    IPC分类号: H01L21/308 H01L21/768

    摘要: A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure.

    摘要翻译: 形成多层台阶图案结构的方法包括在基板上形成具有交替的绝缘夹层和牺牲层的堆叠结构。 第一光致抗蚀剂图案形成在堆叠结构上。 通过使用第一光致抗蚀剂图案作为蚀刻掩模蚀刻层叠结构的部分来形成第一预备步骤图案结构。 钝化层图案形成在第一光致抗蚀剂图案和第一初步步骤图案结构的上表面上。 通过去除由钝化层图案暴露的第一光致抗蚀剂图案的侧壁部分形成第二光致抗蚀剂图案。 通过使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻暴露的绝缘夹层和下面的牺牲层来形成第二初步步骤图案结构。 可以在第二预备步骤图案结构上重复上述步骤以形成多层台阶图案结构。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US09214409B2

    公开(公告)日:2015-12-15

    申请号:US13786853

    申请日:2013-03-06

    摘要: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

    摘要翻译: 提供一种半导体器件。 半导体器件包括设置在半导体衬底上的导电图案。 设置在导电图案上并且彼此位于相同水平面的第一和第二导电线。 隔离图案设置在第一和第二导线之间。 提供穿过第一导线和导电图案的第一垂直结构。 提供穿过第二导线和导电图案的第二垂直结构。 提供穿过导电图案并与隔离图案接触的辅助图案。