Layout decomposition methods and systems

    公开(公告)号:US09874810B2

    公开(公告)日:2018-01-23

    申请号:US15135041

    申请日:2016-04-21

    CPC classification number: G03F1/70 G03F1/68

    Abstract: A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.

    Electronic design automation method and apparatus thereof

    公开(公告)号:US09836565B2

    公开(公告)日:2017-12-05

    申请号:US14824529

    申请日:2015-08-12

    Inventor: Dae-Kwon Kang

    CPC classification number: G06F17/5022 G06F17/5045 G06F17/505

    Abstract: Provided are an electronic design automation apparatus and method. The electronic design automation method includes: loading, by a processor, a rule file having limitations on a reference design file; extracting, by the processor, a plurality of unit operations for respectively performing the limitations from the loaded file; and automatically forming, by the processor, a flowchart corresponding to the rule file based on relations between the plurality of unit operations.

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