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公开(公告)号：US11935835B2
公开(公告)日：2024-03-19
申请号：US17120616
申请日：2020-12-14
发明人： Hyo-Jin Kim , Chang-Hwa Kim , Hwi-Chan Jun , Chul-Hong Park , Jae-Seok Yang , Kwan-Young Chun
IPC分类号： H01L23/535 , H01L21/768 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/06 , H01L29/08 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L23/535 , H01L21/76826 , H01L21/76829 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823475 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/0649 , H01L29/0847 , H01L29/41791 , H01L29/66545 , H01L29/785 , H01L21/76831 , H01L21/76889 , H01L21/823481
摘要： A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
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公开(公告)号：US10957765B2
公开(公告)日：2021-03-23
申请号：US16051667
申请日：2018-08-01
发明人： Pan-Jae Park , Jae-Seok Yang , Young-Hun Kim , Hae-Wang Lee , Kwan-Young Chun
IPC分类号： H01L29/08 , H01L27/088 , H01L27/02 , H01L27/118 , H01L27/092 , H01L21/8234 , H01L29/78 , H01L29/66 , H01L21/8238
摘要： A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.
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公开(公告)号：US09874810B2
公开(公告)日：2018-01-23
申请号：US15135041
申请日：2016-04-21
发明人： Ji-Young Jung , Dae-Kwon Kang , Dong-Gyun Kim , Jae-Seok Yang , Sung-Wook Hwang
摘要： A layout decomposition method is provided which may include building, a graph including a plurality of nodes and edges from a layout design including a plurality of polygons, wherein the nodes correspond to the polygons of the layout design and the edges identify two nodes disposed close to each other at a distance shorter than a minimum distance among the plurality of nodes, comparing degrees of the plurality of nodes with a reference value, selecting a target node, the degree of which exceeds the reference value, identifying a first and second subgraph based on the target node, performing multi-patterning technology decomposition on the first and second subgraph to acquire a first and second result, and creating first mask layout data corresponding to one portion of the layout design and second mask layout data corresponding to the other portion of the layout design by combining the first and second result.
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公开(公告)号：US09652578B2
公开(公告)日：2017-05-16
申请号：US14674416
申请日：2015-03-31
发明人： Dong-Gyun Kim , Sung-Wook Hwang , Dae-Kwon Kang , Jae-Seok Yang , Ji-Young Jung
IPC分类号： G06F17/50 , H01L27/02 , H01L21/308
CPC分类号： G06F17/5081 , G06F17/5063 , G06F17/5068 , H01L21/3086 , H01L27/0207
摘要： A layout design method may include receiving predetermined values related to first to third normal fin designs extending in a first direction and arranged in parallel in a second direction perpendicular to the first direction, generating dummy fin designs based on the predetermined values, generating mandrel candidate designs based on the first to third normal fin designs and the dummy fin designs, decomposing the mandrel candidate designs to first and second mandrel mask designs, and generating a final mandrel mask design using one of the first and second mandrel mask designs that satisfies a predetermined condition. A first interval distance in the second direction between the first normal fin design and the second normal fin design may be different from a second interval distance in the second direction between the second normal fin design and the third normal fin design.
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5.发明授权公开(公告)号：US11461521B2
公开(公告)日：2022-10-04
申请号：US16401820
申请日：2019-05-02
IPC分类号： G06F30/327 , H01L27/02 , G06F30/398
摘要： An integrated circuit including a standard cell includes: a plurality of first wells extending in a first horizontal direction with a first width and of a first conductivity type; and a plurality of second wells extending in the first horizontal direction with a second width and having a second conductivity type, wherein the plurality of first wells and the plurality of second wells are alternately arranged in a second horizontal direction that is orthogonal to the first horizontal direction, and when m and n are integers greater than or equal to 3, the standard cell has a length in the second horizontal direction, the length being equal to a sum of m times a half of the first width and n times a half of the second width.
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公开(公告)号：US20190123140A1
公开(公告)日：2019-04-25
申请号：US16051667
申请日：2018-08-01
发明人： Pan-Jae Park , Jae-Seok Yang , Young-Hun KIM , Hae-Wang LEE , Kwan-Young CHUN
IPC分类号： H01L29/08 , H01L21/8234 , H01L29/66 , H01L27/088 , H01L27/02 , H01L29/78
摘要： A semiconductor device is provided including a substrate, a first gate structure, a first contact plug and a power rail. The substrate includes first and second cell regions extending in a first direction, and a power rail region connected to each of opposite ends of the first and second cell regions in a second direction. The first gate structure extends in the second direction from a boundary area between the first and second cell regions to the power rail region. The first contact plug is formed on the power rail region, and contacts an upper surface of the first gate structure. The power rail extends in the first direction on the power rail region, and is electrically connected to the first contact plug. The power rail supplies a turn-off signal to the first gate structure through the first contact plug to electrically insulate the first and second cell regions.
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公开(公告)号：US09841672B2
公开(公告)日：2017-12-12
申请号：US14690073
申请日：2015-04-17
发明人： Dae-Kwon Kang , Jae-Seok Yang , Sung-Wook Hwang , Dong-Gyun Kim , Ji-Young Jung
CPC分类号： G03F1/70 , G03F7/70433 , G03F7/70466
摘要： A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.
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公开(公告)号：US12068326B2
公开(公告)日：2024-08-20
申请号：US18176463
申请日：2023-02-28
发明人： Young-Hun Kim , Jae-Seok Yang , Hae-Wang Lee
IPC分类号： H01L27/118 , H01L21/8238 , H01L27/02
CPC分类号： H01L27/11807 , H01L21/823814 , H01L21/823878 , H01L27/0207 , H01L2027/11829 , H01L2027/11861 , H01L2027/11864 , H01L2027/11881
摘要： A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.
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公开(公告)号：US11600639B2
公开(公告)日：2023-03-07
申请号：US17087321
申请日：2020-11-02
发明人： Young-Hun Kim , Jae-Seok Yang , Hae-Wang Lee
IPC分类号： H01L27/118 , H01L21/8238 , H01L27/02
摘要： A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.
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公开(公告)号：US10886227B2
公开(公告)日：2021-01-05
申请号：US16217220
申请日：2018-12-12
发明人： Hyo-Jin Kim , Chang-Hwa Kim , Hwi-Chan Jun , Chui-Hong Park , Jae-Seok Yang , Kwan-Young Chun
IPC分类号： H01L23/535 , H01L27/088 , H01L21/84 , H01L27/12 , H01L21/768 , H01L29/08 , H01L21/8234 , H01L29/06 , H01L29/417 , H01L29/66 , H01L29/78
摘要： A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.
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