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公开(公告)号：US10911032B2
公开(公告)日：2021-02-02
申请号：US16524609
申请日：2019-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Chul Hwang , Min-Su Kim , Dae-Seong Lee
IPC: H03K3/012 , H03K3/3562 , H03K3/356
Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.
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公开(公告)号：US11869884B2
公开(公告)日：2024-01-09
申请号：US17559152
申请日：2021-12-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Kyu Ryu , Min-Su Kim , Yong-Geol Kim , Dae-Seong Lee
IPC: H01L27/00 , H01L27/02 , H01L23/552 , G03F1/36 , H01L27/118 , G06F30/398
CPC classification number: H01L27/0207 , G03F1/36 , G06F30/398 , H01L23/552 , H01L27/11807 , H01L2027/11874 , H01L2027/11881 , H01L2027/11892
Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.
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公开(公告)号：US20180145661A1
公开(公告)日：2018-05-24
申请号：US15669072
申请日：2017-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Chul HWANG , Min-Su Kim , Dae-Seong Lee
CPC classification number: H03K3/012 , H03K3/356182 , H03K3/35625
Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.
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公开(公告)号：US11239227B2
公开(公告)日：2022-02-01
申请号：US16105165
申请日：2018-08-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Kyu Ryu , Min-Su Kim , Yong-Geol Kim , Dae-Seong Lee
IPC: H01L23/00 , H01L27/02 , H01L23/552 , G03F1/36 , H01L27/118 , G06F30/398
Abstract: A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.
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公开(公告)号：US10957683B2
公开(公告)日：2021-03-23
申请号：US16250000
申请日：2019-01-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Seong Lee , Ah-Reum Kim , Min-Su Kim , Jong-Kyu Ryu
IPC: H01L27/02 , H01L23/50 , H01L27/092 , G06F30/392 , G06F30/394
Abstract: An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.
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Patent Agency Ranking
公开(公告)号：US09537470B2
公开(公告)日：2017-01-03
申请号：US14824302
申请日：2015-08-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chung-Hee Kim , Min-Su Kim , Ji-Kyum Kim , Emil Kagramanyan , Dae-Seong Lee , Gun-Ok Jung , Uk-Rae Cho
CPC classification number: H03K3/0372 , H03K3/0375
Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.
Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。
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公开(公告)号：US10353000B2
公开(公告)日：2019-07-16
申请号：US15479310
申请日：2017-04-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Doo-Seok Yoon , Min-Su Kim , Chung-Hee Kim , Dae-Seong Lee , Hyun Lee , Matthew Berzins , James Lim
IPC: G01R31/3177 , H03K3/037 , G01R31/317
Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.
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公开(公告)号：US10184984B2
公开(公告)日：2019-01-22
申请号：US15140720
申请日：2016-04-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyun-Chul Hwang , Dae-Seong Lee , Min-Su Kim
IPC: G01R31/28 , G01R31/3185
Abstract: An integrated circuit and an electronic apparatus including the same. The electronic apparatus includes a scan input processing circuit, a selection circuit and a scanning circuit. The scan input processing unit is configured to output one of a scan input and a first logical value in response to a scan enable signal. The selection unit is configured to select one of an output of the scan input processing unit or a data input in response to the scan enable signal. The scan element comprises a flip-flop configured to store an output of the selection unit.
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公开(公告)号：US10396761B2
公开(公告)日：2019-08-27
申请号：US15669072
申请日：2017-08-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Chul Hwang , Min-Su Kim , Dae-Seong Lee
IPC: H03K3/012 , H03K3/356 , H03K3/3562
Abstract: A flip-flop includes a first node charging circuit configured to charge a first node with inverted input data generated by inverting input data, a second node charging circuit configured to charge a second node with the input data, and first through eighth NMOS transistors. The flip-flop is configured to latch the input data at rising edges of a clock signal and output latched input data as output data. The flip-flop includes an internal circuit configured to charge a sixth node with inverted input data generated by inverting the latched input data.
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公开(公告)号：US09130550B2
公开(公告)日：2015-09-08
申请号：US14295802
申请日：2014-06-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Chung-Hee Kim , Min-Su Kim , Ji-Kyum Kim , Emil Kagramanyan , Dae-Seong Lee , Gun-Ok Jung , Uk-Rae Cho
CPC classification number: H03K3/0372 , H03K3/0375
Abstract: Provided are a semiconductor device and a method for operating a semiconductor device. The semiconductor device includes a clock generating unit receiving a reference clock and generating first and second clocks that are different from each other from the reference clock; a first latch configured to receive input data based on the first clock and to output the input data as first output data; and a second latch configured to receive the first output data based on the second clock and to output the first output data as second output data, wherein a first edge of the first clock does not overlap a first edge of the second clock, and at least a part of a second edge of the first clock overlaps a second edge of the second clock.
Abstract translation: 提供半导体器件和用于操作半导体器件的方法。 所述半导体器件包括：时钟生成单元，接收参考时钟;产生与所述参考时钟不同的第一和第二时钟; 第一锁存器，被配置为基于所述第一时钟接收输入数据并将所述输入数据输出为第一输出数据; 以及第二锁存器，被配置为基于所述第二时钟接收所述第一输出数据并将所述第一输出数据输出为第二输出数据，其中所述第一时钟的第一边缘不与所述第二时钟的第一边缘重叠，并且至少 第一时钟的第二边缘的一部分与第二时钟的第二边缘重叠。
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