公开(公告)号：US20250072087A1

公开(公告)日：2025-02-27

申请号：US18583269

申请日：2024-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook PARK ,  Sangmin KANG ,  Changwoo SEO ,  Suyoun SONG ,  Dain LEE

IPC: H01L29/417 ,  H01L23/528

Abstract: A semiconductor device may include first and second active patterns, each including a center portion and an edge portion, the center portion of the first active pattern and the edge portion of the second active pattern adjacent to each other, a device isolation pattern between the first and second active patterns, a bit line node contact on the center portion of the first active pattern, a bit line on the bit line node contact, a storage node contact on the edge portion of the second active pattern, a bit line spacer between the bit line and the storage node contact, and a gapfill insulating pattern between a lower portion of the bit line spacer and the storage node contact. The center portion of the first active pattern may include a center oxide region in an upper portion thereof.

公开(公告)号：US20220093387A1

公开(公告)日：2022-03-24

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain LEE ,  Yoongoo KANG ,  Wonseok YOO ,  Jinwon MA ,  Kyungwook PARK ,  Changwoo SEO ,  Suyoun SONG

IPC: H01L21/02 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.

公开(公告)号：US20220246620A1

公开(公告)日：2022-08-04

申请号：US17723218

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20210066304A1

公开(公告)日：2021-03-04

申请号：US16837274

申请日：2020-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo KANG ,  Wonseok YOO ,  Hokyun AN ,  Kyungwook PARK ,  Dain LEE

IPC: H01L27/108 ,  G11C5/06 ,  H01L29/06

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.