公开(公告)号：US11205485B2

公开(公告)日：2021-12-21

申请号：US16935598

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim ,  Min-Su Kim ,  Deok-Woo Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

公开(公告)号：US10431314B2

公开(公告)日：2019-10-01

申请号：US15996485

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim ,  Deok-Woo Lee ,  Dong-Hun Kwak

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/30 ,  G11C16/14 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/1157

Abstract: A non-volatile memory device includes multiple word lines, and a voltage generator. Some of the word lines correspond to a deterioration area. The voltage generator is configured to generate a program voltage provided to multiple memory cells through the word lines. Control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the word lines. The deterioration area includes word lines of a first group and word lines of a second group. The control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and to control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.

公开(公告)号：US20190156896A1

公开(公告)日：2019-05-23

申请号：US16043964

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Yoon Park ,  Wan-Dong Kim ,  Seung-Bum Kim ,  Deok-Woo Lee ,  You-Se Kim ,  Se-Hwan Park ,  Jin-Woo Park

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3445 ,  G11C29/52

Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

公开(公告)号：US11315646B2

公开(公告)日：2022-04-26

申请号：US17141408

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim ,  Min-Su Kim ,  Deok-Woo Lee

IPC: G11C16/34 ,  G11C16/12 ,  G11C16/24 ,  G11C16/08

Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

公开(公告)号：US11049577B2

公开(公告)日：2021-06-29

申请号：US16299684

申请日：2019-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim ,  Min-Su Kim ,  Deok-Woo Lee

IPC: G11C16/34 ,  G11C16/12 ,  G11C16/24 ,  G11C16/08

Abstract: A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.