公开(公告)号：US10712954B2

公开(公告)日：2020-07-14

申请号：US16111813

申请日：2018-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Bum Kim

IPC: G06F3/06 ,  G11C16/30 ,  G11C5/14 ,  H01L27/1157 ,  H01L27/11565 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C29/52 ,  G11C29/04 ,  G11C29/12 ,  H01L27/11582

Abstract: Nonvolatile memory device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory blocks, the memory blocks including a plurality of memory cells coupled to word-lines respectively, the word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selected by sub-block unit smaller than one memory block. The control circuit divides sub-blocks of a first memory block into at least one bad sub-block and at least one normal sub-block based on error occurrence frequency of each of the sub-blocks, and applies different program/erase cycles to the at least one bad sub-block and the at least one normal sub-block based on a command and an address provided from external to the nonvolatile memory device. The at least one bad sub-block and the at least one normal sub-block are adjacent each other.

公开(公告)号：US09164889B2

公开(公告)日：2015-10-20

申请号：US13755144

申请日：2013-01-31

Applicant: SAMSUNG Electronics Co., Ltd.

Inventor： Seung-Bum Kim ,  Jaeyong Jeong ,  Kitae Park

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/56 ,  G11C7/10 ,  G11C16/10 ,  G06F11/10

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5641

Abstract: A memory system includes a nonvolatile memory device having a first data area storing M-bit data using a buffer program operation and a second data area storing N-bit data (N being an integer larger than M) using a main program operation and a memory controller configured to control the nonvolatile memory device. When a main program operation using data stored at the first and second data areas is required, the memory controller calculates values indicating a performance of the required main program operation to be executed according to a plurality of main program manners, selects one of the plurality of main program manners based on the calculated values, and controls the nonvolatile memory device to perform the required main program operation according to the selected main program manner.

Abstract translation: 存储器系统包括：非易失性存储器件，其具有使用缓冲器程序操作存储M位数据的第一数据区和使用主程序操作存储N位数据（N大于M的整数）的第二数据区;存储器 控制器被配置为控制非易失性存储器件。 当需要使用存储在第一和第二数据区域的数据的主程序操作时，存储器控制器根据多个主程序方式计算指示要执行的所需主程序操作的性能的值，选择多个 基于计算值的主程序方式，并且根据选择的主程序方式控制非易失性存储器件执行所需的主程序操作。

公开(公告)号：US10431314B2

公开(公告)日：2019-10-01

申请号：US15996485

申请日：2018-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim ,  Deok-Woo Lee ,  Dong-Hun Kwak

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/30 ,  G11C16/14 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/1157

Abstract: A non-volatile memory device includes multiple word lines, and a voltage generator. Some of the word lines correspond to a deterioration area. The voltage generator is configured to generate a program voltage provided to multiple memory cells through the word lines. Control logic implemented by the non-volatile memory device is configured to control a program operation and an erase operation on the word lines. The deterioration area includes word lines of a first group and word lines of a second group. The control logic is configured to control a program sequence so that each of the word lines of the second group is programmed after an adjacent word line of the first group is programmed, and to control a distribution so that a threshold voltage level corresponding to an erase state of each of the word lines of the first group is higher than a threshold voltage level corresponding to an erase state of each of the word lines of the second group.

公开(公告)号：US20190156896A1

公开(公告)日：2019-05-23

申请号：US16043964

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Yoon Park ,  Wan-Dong Kim ,  Seung-Bum Kim ,  Deok-Woo Lee ,  You-Se Kim ,  Se-Hwan Park ,  Jin-Woo Park

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3445 ,  G11C29/52

Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

公开(公告)号：US09418747B2

公开(公告)日：2016-08-16

申请号：US14227314

申请日：2014-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Ku Kang ,  Seung-Bum Kim

IPC: G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3459

Abstract: A nonvolatile memory device comprises a memory cell array comprising multiple memory cells disposed at intersections of corresponding word lines and bitlines, and multiple page buffers connected to the bitlines, respectively, and performing consecutive verify read operations on selected memory cells programmed in first to N-th logic states (N>2), wherein, in the consecutive verify read operations, the bitlines are placed in a precharged state by precharging them to a first level during a verification period of memory cells programmed in the first logic state, are maintained in the precharged state during verification periods of memory cells programmed in the second to (N−1)-th logic states, and are discharged after a verification period of memory cells programmed in the N-th logic state.

Abstract translation: 非易失性存储器件包括存储单元阵列，该存储单元阵列包括设置在相应字线和位线的交点处的多个存储器单元，以及分别连接到位线的多页缓冲器，以及对在第一至第N编程中选定的存储器单元执行连续验证读操作， 逻辑状态（N> 2），其中，在连续验证读取操作中，通过在第一逻辑状态中编程的存储器单元的验证周期期间将位线预先充电到第一电平，将位线置于预充电状态 以第二到第（N-1）逻辑状态编程的存储器单元的验证期间的预充电状态，并且在以第N逻辑状态编程的存储单元的验证周期之后放电。

公开(公告)号：US08717832B2

公开(公告)日：2014-05-06

申请号：US14048944

申请日：2013-10-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Bum Kim

IPC: G11C7/00

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483

Abstract: Within a non-volatile memory device, a read operation directed to a nonvolatile memory cell having a positive threshold voltage applies a positive read voltage to a selected word line and a first control signal to a page buffer connected to a selected bit line, but if the memory cell has a negative threshold voltage the read operation applies a negative read voltage to the selected word line and a second control signal to the page buffer different from the first control signal.

Abstract translation: 在非易失性存储器件中，针对具有正阈值电压的非易失性存储单元的读取操作将正读取电压施加到所选字线和第一控制信号到连接到所选位线的页缓冲器，但如果 存储单元具有负的阈值电压，读取操作将一个负的读取电压施加到所选择的字线，并且将第二个控制信号施加到与第一个控制信号不同的页面缓冲器。

公开(公告)号：US11294580B2

公开(公告)日：2022-04-05

申请号：US17033077

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim

IPC: G06F3/06 ,  G11C5/14 ,  H01L27/1157 ,  H01L27/11565 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C29/52 ,  G11C16/30 ,  H01L27/11582 ,  G11C29/04 ,  G11C29/12

Abstract: A nonvolatile memory device includes a memory cell region having a first metal pad and a peripheral circuit region having a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a a memory cell array in the memory cell region and an address decoder in the peripheral circuit region. The memory cell array includes memory blocks, and each memory block includes memory cells coupled to word-lines respectively. The word-lines are stacked vertically on a substrate, and some memory cells of the plurality of memory cells are selectable by a sub-block unit smaller than one memory block of the plurality of memory blocks. The address decoder applies an erase voltage to each of sub-blocks in a first memory block of the plurality of memory blocks through the first metal pad and the second metal pad.

公开(公告)号：US11205485B2

公开(公告)日：2021-12-21

申请号：US16935598

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Bum Kim ,  Min-Su Kim ,  Deok-Woo Lee

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

公开(公告)号：US10734082B2

公开(公告)日：2020-08-04

申请号：US16275108

申请日：2019-02-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Han-Jun Lee ,  Seung-Bum Kim ,  Chul-Bum Kim ,  Seung-Jae Lee

IPC: G11C16/28 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14 ,  G11C16/24 ,  G11C7/18 ,  G11C16/08 ,  G11C29/08 ,  G11C7/04

Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.

公开(公告)号：US20200098436A1

公开(公告)日：2020-03-26

申请号：US16364588

申请日：2019-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Bum Kim ,  II-Han Park ,  Ji-Young Lee ,  Su-Chang Jeon

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/24 ,  G11C16/10 ,  G11C16/34 ,  G11C16/14 ,  G06F11/10 ,  G11C29/52

Abstract: Nonvolatile memory device includes a memory cell array including pages, each of the pages including memory cells storing data bits, each of the data bits being selectable by a different threshold voltage, a page buffer circuit coupled to the memory cell array through bit-lines, the page buffer circuit including page buffers to sense data from selected memory cells, and perform a first read operation and a second read operation, each including two sequential sensing operations to determine one data state, and each of the page buffers including a latch configured to sequentially store results of the two sequential sensing operations, and a control circuit to control the page buffers to store a result of the first read operation, reset the latches after completion of the first read operation, and perform the second read operation based on a valley determined based on the result of the first read operation.