公开(公告)号：US20190156896A1

公开(公告)日：2019-05-23

申请号：US16043964

申请日：2018-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-Yoon Park ,  Wan-Dong Kim ,  Seung-Bum Kim ,  Deok-Woo Lee ,  You-Se Kim ,  Se-Hwan Park ,  Jin-Woo Park

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3445 ,  G11C29/52

Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

公开(公告)号：US11804268B2

公开(公告)日：2023-10-31

申请号：US17525934

申请日：2021-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Hwan Park ,  Wan-Dong Kim

IPC: G11C11/34 ,  G11C16/24 ,  G11C16/34 ,  G06F13/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/14 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/24 ,  G06F13/1668 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418 ,  G06F2213/0024 ,  G11C16/14 ,  G11C2211/5648 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

公开(公告)号：US12190963B2

公开(公告)日：2025-01-07

申请号：US18235838

申请日：2023-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Hwan Park ,  Wan-Dong Kim

IPC: G11C11/34 ,  G06F13/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/14 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A memory device may include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block may include first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device mat be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

公开(公告)号：US20190074065A1

公开(公告)日：2019-03-07

申请号：US16004770

申请日：2018-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Hwan Park ,  Wan-Dong Kim

IPC: G11C16/24 ,  G11C16/08 ,  G11C16/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G06F13/16

Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

公开(公告)号：US11276471B2

公开(公告)日：2022-03-15

申请号：US17207657

申请日：2021-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Hwan Park ,  Wan-Dong Kim

IPC: G11C11/34 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  G06F13/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

公开(公告)号：US11232841B2

公开(公告)日：2022-01-25

申请号：US17010681

申请日：2020-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Hwan Park ,  Wan-Dong Kim

IPC: G11C11/34 ,  G11C16/24 ,  G11C16/34 ,  G06F13/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11582 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

公开(公告)号：US10971235B2

公开(公告)日：2021-04-06

申请号：US16840290

申请日：2020-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se-Hwan Park ,  Wan-Dong Kim

IPC: G11C11/34 ,  G11C16/24 ,  G11C11/56 ,  G11C16/34 ,  G06F13/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device can include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block includes first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device can be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

公开(公告)号：US10573386B2

公开(公告)日：2020-02-25

申请号：US16035958

申请日：2018-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wan-Dong Kim ,  Tae-Hyun Kim ,  Sang-Wan Nam ,  Sang-Soo Park ,  Jae-Yong Jeong

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/28 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/32 ,  G11C5/06

Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.