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1.发明申请公开(公告)号：US20190080428A1
公开(公告)日：2019-03-14
申请号：US16007628
申请日：2018-06-13
发明人： Jeong-joon Yoo , Taek-hyun Kim , Dong-hoon Yoo
CPC分类号： G06T1/20 , G06T1/60 , G06T11/203 , G06T11/40
摘要： Provided are a graphics processing unit and a graphics processing method for performing path rendering. The graphics processing method may include receiving object information including primitive information regarding the object; generating a primitive mask with respect to respective pixels, the primitive mask corresponding to the primitive information and including a plurality of bits; generating, based on the primitive mask, winding numbers with respect to the respective pixels; and rendering the pixels, based on the winding numbers.
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公开(公告)号：US11100686B2
公开(公告)日：2021-08-24
申请号：US16576353
申请日：2019-09-19
发明人： Jeong-joon Yoo , Young-sam Shin , Dong-hoon Yoo
摘要： An apparatus configured to render an object including a path includes a storage circuit, an arithmetic circuit configured to determine a direction of a plurality of primitives included in the path based on path data, generate primitive direction information, store the primitive direction information in the storage circuit, and generate a winding number of each of a plurality of pixels using the stored primitive direction information, and a determination circuit configured to determine whether a shading operation is to be performed based on the generated winding number.
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3.发明授权公开(公告)号：US10409351B2
公开(公告)日：2019-09-10
申请号：US15788293
申请日：2017-10-19
发明人： Bernhard Egger , Younghyun Cho , Su-Rim Oh , Dong-hoon Yoo
IPC分类号： G06F1/32 , G06F1/28 , G06F1/20 , G06F1/324 , G06F1/3296
摘要： Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
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4.发明申请APPARATUS AND METHOD FOR GENERATING VLIW, AND PROCESSOR AND METHOD FOR PROCESSING VLIW 审中-公开用于生成VLIW的装置和方法，以及处理器和处理VLIW的方法公开(公告)号：US20140052960A1
公开(公告)日：2014-02-20
申请号：US14064497
申请日：2013-10-28
发明人： Bernhard Egger , Soo-jung Ryu , Dong-hoon Yoo , Il-hyun Park
IPC分类号： G06F15/82
CPC分类号： G06F15/82 , G06F9/30072 , G06F9/3853
摘要： An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.
摘要翻译： 本文提供了一种用于生成支持预定执行的非常长的指令字（VLIW）命令和用于处理VLIW的VLIW处理器和方法的装置和方法。 VLIW命令包括由并行执行的多个指令形成的指令束和指示预测执行的单个值，并且使用用于生成VLIW命令的装置和方法生成。 根据指示预先执行的值，VLIW处理器并行地解码指令束并且并行地执行包括在解码指令束中的指令。
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公开(公告)号：US11126535B2
公开(公告)日：2021-09-21
申请号：US16529926
申请日：2019-08-02
发明人： Young-sam Shin , Dong-hoon Yoo , Jeong-joon Yoo
摘要： A computing system is provided. The computing system includes: a memory configured to store a shader program; and a graphics processing unit (GPU) configured to obtain the shader program stored in the memory in a profile mode, the GPU being configured to perform: inserting, into the shader program, one or more monitor associative codes; compiling the shader program, into which the one or more monitor associative codes are inserted, into a language that is capable of being processed by a plurality of cores; and obtaining a runtime performance characteristic of the shader program by executing the compiled shader program and the one or more monitor associative codes.
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6.发明申请公开(公告)号：US20190339760A1
公开(公告)日：2019-11-07
申请号：US16518421
申请日：2019-07-22
发明人： Bernhard Egger , Younghyun CHO , Su-Rim Oh , Dong-hoon Yoo
IPC分类号： G06F1/28 , G06F1/20 , G06F1/324 , G06F1/3296
摘要： Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
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公开(公告)号：US09342480B2
公开(公告)日：2016-05-17
申请号：US14064497
申请日：2013-10-28
发明人： Bernhard Egger , Soo-jung Ryu , Dong-hoon Yoo , Il-hyun Park
CPC分类号： G06F15/82 , G06F9/30072 , G06F9/3853
摘要： An apparatus and method for generating a very long instruction word (VLIW) command that supports predicated execution, and a VLIW processor and method for processing a VLIW are provided herein. The VLIW command includes an instruction bundle formed of a plurality of instructions to be executed in parallel and a single value indicating predicated execution, and is generated using the apparatus and method for generating a VLIW command. The VLIW processor decodes the instruction bundle and executes the instructions, which are included in the decoded instruction bundle, in parallel, according to the value indicating predicated execution.
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8.发明授权公开(公告)号：US11301016B2
公开(公告)日：2022-04-12
申请号：US16518421
申请日：2019-07-22
发明人： Bernhard Egger , Younghyun Cho , Su-Rim Oh , Dong-hoon Yoo
IPC分类号： G06F1/28 , G06F1/20 , G06F1/324 , G06F1/3296 , G06F1/3203 , G06F1/3234
摘要： Provided are computing devices, each including a plurality of cores, and methods of allocating power to the plurality of cores. The computing device includes: a control core group including a plurality of control cores, the control core group configured to allocate a power budget to processing cores according to an energy management policy and state information of the processing cores, and transmit the allocated power budget to at least one of a lower control core and the processing cores; and a processing core group including at least one or more of the processing cores, the processing core group configured to perform computations based on the power budget allocated by the control core group, and transmit state information of the processing cores to the control core group, the state information of the processing cores having been modified based on the computations performed.
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9.发明授权公开(公告)号：US10776896B2
公开(公告)日：2020-09-15
申请号：US16007628
申请日：2018-06-13
发明人： Jeong-joon Yoo , Taek-hyun Kim , Dong-hoon Yoo
摘要： Provided are a graphics processing unit and a graphics processing method for performing path rendering. The graphics processing method may include receiving object information including primitive information regarding the object; generating a primitive mask with respect to respective pixels, the primitive mask corresponding to the primitive information and including a plurality of bits; generating, based on the primitive mask, winding numbers with respect to the respective pixels; and rendering the pixels, based on the winding numbers.
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