公开(公告)号：US10284360B2

公开(公告)日：2019-05-07

申请号：US15415336

申请日：2017-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongho Choi ,  Younwoong Chung

IPC: H03K5/133 ,  H04L7/00 ,  H03L7/08 ,  H03L7/099 ,  H03K5/00

Abstract: An electronic circuit receives transmission signals from three or more communication lines. The electronic circuit includes a clock-data recovery circuit and a control value generation circuit. The clock-data recovery circuit outputs a recovered clock based on a transition generated in reception signals. The clock-data recovery circuit outputs recovered signals based on the recovered clock and the reception signals. The recovered clock has a first edge in response to the transition generated in the reception signals. The recovered clock has a second edge in response to a reset signal generated based on a delay of the recovered clock. The delay of the recovered clock is adjusted based on a control value provided from the control value generation circuit. The control value is adjusted based on change of a communication condition.

公开(公告)号：US12119829B2

公开(公告)日：2024-10-15

申请号：US18308754

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Choi ,  Jaeduk Han ,  Yongho Song ,  Youngho Kwak ,  Gaeryun Sung ,  Dongju Yang ,  Kwanghee Choi ,  Hyeongmin Seo

IPC: H03L7/08 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03L7/0807 ,  H03L7/091 ,  H03L7/0998

Abstract: A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.

公开(公告)号：US20230421161A1

公开(公告)日：2023-12-28

申请号：US18308754

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Choi ,  Jaeduk Hun ,  Yongho Song ,  Youngho Kwak ,  Gaeryun Sung ,  Dongju Yang ,  Kwanghee Choi ,  Hyeongmin Seo

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/091

CPC classification number: H03L7/0807 ,  H03L7/0998 ,  H03L7/091

Abstract: A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.