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1.发明授权公开(公告)号：US12119829B2
公开(公告)日：2024-10-15
申请号：US18308754
申请日：2023-04-28
发明人： Dongho Choi , Jaeduk Han , Yongho Song , Youngho Kwak , Gaeryun Sung , Dongju Yang , Kwanghee Choi , Hyeongmin Seo
CPC分类号： H03L7/0807 , H03L7/091 , H03L7/0998
摘要： A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.
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2.发明公开公开(公告)号：US20230421161A1
公开(公告)日：2023-12-28
申请号：US18308754
申请日：2023-04-28
发明人： Dongho Choi , Jaeduk Hun , Yongho Song , Youngho Kwak , Gaeryun Sung , Dongju Yang , Kwanghee Choi , Hyeongmin Seo
CPC分类号： H03L7/0807 , H03L7/0998 , H03L7/091
摘要： A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.
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