公开(公告)号：US11733883B2

公开(公告)日：2023-08-22

申请号：US17511198

申请日：2021-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngho Kwak ,  Hojun Shim ,  Kwanghee Choi

IPC: G06F3/06 ,  G06F1/3206 ,  G06F13/10

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F3/0658 ,  G06F3/0679 ,  G06F13/102 ,  G06F2213/0026

Abstract: A storage device comprises a controller and a plurality of nonvolatile memory devices. Maintenance conditions of the nonvolatile memory devices are monitored internally by the storage device. Upon determining that a maintenance condition is satisfied, the storage device notifies an external host. The controller may perform the maintenance operations on the plurality of nonvolatile memory devices with little disruption to the host and assure data is reliably maintained by the nonvolatile memory devices.

公开(公告)号：US11175835B2

公开(公告)日：2021-11-16

申请号：US16447995

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngho Kwak ,  Hojun Shim ,  Kwanghee Choi

IPC: G06F3/06 ,  G06F1/3206 ,  G06F13/10

Abstract: A storage device comprises a controller and a plurality of nonvolatile memory devices. Maintenance conditions of the nonvolatile memory devices are monitored internally by the storage device. Upon determining that a maintenance condition is satisfied, the storage device notifies an external host. The controller may perform the maintenance operations on the plurality of nonvolatile memory devices with little disruption to the host and assure data is reliably maintained by the nonvolatile memory devices.

公开(公告)号：US12119829B2

公开(公告)日：2024-10-15

申请号：US18308754

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Choi ,  Jaeduk Han ,  Yongho Song ,  Youngho Kwak ,  Gaeryun Sung ,  Dongju Yang ,  Kwanghee Choi ,  Hyeongmin Seo

IPC: H03L7/08 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03L7/0807 ,  H03L7/091 ,  H03L7/0998

Abstract: A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.

公开(公告)号：US20230421161A1

公开(公告)日：2023-12-28

申请号：US18308754

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Choi ,  Jaeduk Hun ,  Yongho Song ,  Youngho Kwak ,  Gaeryun Sung ,  Dongju Yang ,  Kwanghee Choi ,  Hyeongmin Seo

IPC: H03L7/08 ,  H03L7/099 ,  H03L7/091

CPC classification number: H03L7/0807 ,  H03L7/0998 ,  H03L7/091

Abstract: A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.