公开(公告)号：US12119829B2

公开(公告)日：2024-10-15

申请号：US18308754

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Choi ,  Jaeduk Han ,  Yongho Song ,  Youngho Kwak ,  Gaeryun Sung ,  Dongju Yang ,  Kwanghee Choi ,  Hyeongmin Seo

IPC: H03L7/08 ,  H03L7/091 ,  H03L7/099

CPC classification number: H03L7/0807 ,  H03L7/091 ,  H03L7/0998

Abstract: A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.

公开(公告)号：US20230403010A1

公开(公告)日：2023-12-14

申请号：US18175795

申请日：2023-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunyoon Cho ,  Eunseok Shin ,  Youngdon Choi ,  Jaeduk Han ,  Hyuntae Kim ,  Jeonghyu Yang ,  Sanghun Lee

IPC: H03K19/096 ,  H03K5/15

CPC classification number: H03K19/096 ,  H03K5/15013

Abstract: A parallel-to-serial converter includes first to fourth input nodes configured to receive first to fourth data input signals, respectively, and an output node configured to output a data output signal. First to fourth logic circuits are provided, which are configured to electrically couple respective ones of the first to fourth input nodes one-at-a-time to the output node, in synchronization with first to fourth clock signals. The first logic circuit includes a first input circuit, a second input circuit, and an output circuit electrically coupled to the first and second input circuits. The output circuit includes a first pull-up transistor and a first pull-down transistor having drain terminals coupled to the output node, a second pull-up transistor connected between a source terminal of the first pull-up transistor and a first power supply node, and a second pull-down transistor connected between a source terminal of the first pull-down transistor and a second power supply node.