公开(公告)号：US09318566B2

公开(公告)日：2016-04-19

申请号：US14159940

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-Kyun Lee ,  Eung-Kyu Lee

IPC: H01L21/336 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/45 ,  H01L29/08

CPC classification number: H01L29/407 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7813

Abstract: In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成沟道层，并且在沟道层中形成沟槽图案。 杂质体形成在沟槽图案之间的沟道层中，并且在沟道层中形成的杂质体中的沟槽图案之间形成沟槽。 源极隔离区域形成在槽的底部的杂质体中，源极区域形成在沟槽的侧壁部分的杂质体中。

公开(公告)号：US08975693B2

公开(公告)日：2015-03-10

申请号：US13683505

申请日：2012-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eung-Kyu Lee ,  Jae-June Jang ,  Hoon Chang ,  Min-Hwan Kim ,  Sung-Ryoul Bae ,  Dong-Eun Jang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.

Abstract translation: 半导体器件包括第一导电类型的半导体衬底，与衬底上的第一导电类型不同的第二导电类型的掩埋层和在掩埋层上的第二导电类型的外延层。 器件还包括在外延层中的第一导电类型的凹穴，外延层中的至少部分地与凹穴阱重叠的第一漂移区，外延层中的与第一漂移区间隔开的第二漂移区， 以及口袋中的第一导电类型的体区。 栅电极设置在体区，口腔和第一漂移区上，并且具有覆盖第一和第二漂移区之间的外延区的边缘。

公开(公告)号：US20140295632A1

公开(公告)日：2014-10-02

申请号：US14159940

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-Kyun Lee ,  Eung-Kyu Lee

IPC: H01L29/66

CPC classification number: H01L29/407 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/7811 ,  H01L29/7813

Abstract: In a method of fabricating a semiconductor device, a channel layer is formed on a substrate, and trench patterns are formed in the channel layer. Impurity bodies are formed in the channel layer between the trench patterns, and grooves are formed between the trench patterns in the impurity bodies formed in the channel layer. Source isolation regions are formed in the impurity bodies at bottom portions of the grooves, and source regions are formed in the impurity bodies at sidewall portions of the grooves.

Abstract translation: 在制造半导体器件的方法中，在衬底上形成沟道层，并且在沟道层中形成沟槽图案。 杂质体形成在沟槽图案之间的沟道层中，并且在沟道层中形成的杂质体中的沟槽图案之间形成沟槽。 源极隔离区域形成在槽的底部的杂质体中，源极区域形成在沟槽的侧壁部分的杂质体中。

公开(公告)号：US20130256794A1

公开(公告)日：2013-10-03

申请号：US13683505

申请日：2012-11-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eung-Kyu Lee ,  Jae-June Jang ,  Hoon Chang ,  Min-Hwan Kim ,  Sung-Ryoul Bae ,  Dong-Eun Jang

IPC: H01L29/78

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66681

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a buried layer a second conductivity type different from the first conductivity type on the substrate and an epitaxial layer of the second conductivity type on the buried layer. The device further includes a pocket well of the first conductivity type in the epitaxial layer, a first drift region in the epitaxial layer at least partially overlapping the pocket well, a second drift region in the epitaxial layer and spaced apart from the first drift region, and a body region of the first conductivity type in the pocket well. A gate electrode is disposed on the body region, the pocket well and the first drift region and has an edge overlying the epitaxial region between the first and second drift regions.

Abstract translation: 半导体器件包括第一导电类型的半导体衬底，与衬底上的第一导电类型不同的第二导电类型的掩埋层和在掩埋层上的第二导电类型的外延层。 器件还包括在外延层中的第一导电类型的凹穴，外延层中的至少部分地与凹穴阱重叠的第一漂移区，外延层中的与第一漂移区间隔开的第二漂移区， 以及口袋中的第一导电类型的体区。 栅电极设置在体区，口腔和第一漂移区上，并且具有覆盖第一和第二漂移区之间的外延区的边缘。