公开(公告)号：US11227870B2

公开(公告)日：2022-01-18

申请号：US16739392

申请日：2020-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H01L27/11578 ,  H01L27/11582 ,  H01L27/1157

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

公开(公告)号：US11716849B2

公开(公告)日：2023-08-01

申请号：US17143216

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong Chung ,  Ho Jin Kim ,  Young-Jin Kwon ,  Dong Seog Eun

IPC: H01L27/11582 ,  H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

公开(公告)号：US11974433B2

公开(公告)日：2024-04-30

申请号：US17575947

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-Heon Kang ,  Tae Hun Kim ,  Jae Ryong Sim ,  Kwang Young Jung ,  Gi Yong Chung ,  Jee Hoon Han ,  Doo Hee Hwang

IPC: H10B43/27 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B43/35

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.