公开(公告)号：US11716849B2

公开(公告)日：2023-08-01

申请号：US17143216

申请日：2021-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gi Yong Chung ,  Ho Jin Kim ,  Young-Jin Kwon ,  Dong Seog Eun

IPC: H01L27/11582 ,  H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  G11C8/14 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

Abstract: A nonvolatile memory device includes a substrate including a cell array region, a first gate electrode including an opening on the cell array region of the substrate, a plurality of second gate electrodes stacked above the first gate electrode and including convex portions having an outward curve extending toward the substrate, and a word line cutting region cutting the opening and the convex portions.

公开(公告)号：US12218062B2

公开(公告)日：2025-02-04

申请号：US18514716

申请日：2023-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyoung Kim ,  Young-Jin Kwon ,  Geun Won Lim

IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

公开(公告)号：US09472568B2

公开(公告)日：2016-10-18

申请号：US14502115

申请日：2014-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoocheol Shin ,  Jaegoo Lee ,  Young-Jin Kwon ,  Jintaek Park

IPC: H01L27/115 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/76802 ,  H01L27/1157 ,  H01L27/11575

Abstract: A semiconductor device is provided as follows. A peripheral circuit structure is disposed on a first substrate. A cell array structure is disposed on the peripheral circuit structure. A second substrate is interposed between the peripheral circuit structure and the cell array structure. The cell array structure includes a stacked structure, a through hole and a vertical semiconductor pattern. The stacked structure includes gate electrodes stacked on the second substrate. The through hole penetrates the stacked structure and the second substrate to expose the peripheral circuit structure. The vertical semiconductor pattern is disposed on the peripheral circuit structure, filling the through hole.

Abstract translation: 如下提供半导体器件。 外围电路结构设置在第一基板上。 电池阵列结构设置在外围电路结构上。 第二基板介于外围电路结构和电池阵列结构之间。 电池阵列结构包括堆叠结构，通孔和垂直半导体图案。 层叠结构包括层叠在第二基板上的栅电极。 通孔贯穿堆叠结构和第二基板，露出外围电路结构。 垂直半导体图案设置在外围电路结构上，填充通孔。

公开(公告)号：US11862566B2

公开(公告)日：2024-01-02

申请号：US17018400

申请日：2020-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun Hyoung Kim ,  Young-Jin Kwon ,  Geun Won Lim

IPC: H01L23/535 ,  H01L21/768 ,  H10B43/27 ,  H10B43/40

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device, in which a cell array region and an extension region are arranged along a first direction, and in which contact regions and through regions are alternately arranged along the first direction in the extension region, including: a mold structure including a plurality of first insulating patterns and a plurality of gate electrodes, which are alternately stacked on a first substrate; a channel structure penetrating the mold structure in the cell array region to intersect the plurality of gate electrodes; respective gate contacts that are on the mold structure in the contact regions and are connected to each of the gate electrodes; and a plurality of second insulating patterns, the second insulating patterns being stacked alternately with the first insulating patterns in the mold structure in the through regions, the plurality of second insulating patterns including a different material from the plurality of first insulating patterns.

公开(公告)号：US10229927B2

公开(公告)日：2019-03-12

申请号：US14725476

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun Lee ,  Jaegoo Lee ,  Young-Jin Kwon ,  Youngwoo Park ,  Jaeduk Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/792 ,  H01L27/1157

Abstract: A semiconductor device includes a lower stack structure including lower gate electrodes and lower insulating layers that are alternately and repeatedly stacked on a substrate. The semiconductor device includes an upper stack structure including upper gate electrodes and upper insulating layers that are alternately and repeatedly stacked on the lower stack structure. A lower channel structure penetrates the lower stack structure. An upper channel structure penetrates and is connected to the upper stack structure. A lower vertical insulator is disposed between the lower stack structure and the lower channel structure. The lower channel structure includes a first vertical semiconductor pattern connected to the substrate, and a first connecting semiconductor pattern disposed on the first vertical semiconductor pattern. The upper channel structure includes a second vertical semiconductor pattern electrically connected to the first vertical semiconductor pattern with the first connecting semiconductor pattern disposed therebetween.