公开(公告)号：US20160042785A1

公开(公告)日：2016-02-11

申请号：US14793053

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Jongsun Park ,  Woong Choi

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C2207/002

Abstract: A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Abstract translation: 存储器件包括包括单端位线结构的存储器单元的第一存储单元阵列，包括单端位线结构的存储单元的第二存储单元阵列，配置为输出所选择的位线的位线电压的参考电压发生器 的第一和第二存储单元阵列作为根据阵列选择信号的感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压;以及差分读出放大器，被配置为放大和输出感测电压 和参考电压。 感测电压和参考电压的逻辑状态彼此互补。

公开(公告)号：US20230134533A1

公开(公告)日：2023-05-04

申请号：US17817435

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsun Park ,  Yunho Jang ,  Seonggeon Park

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: A semiconductor memory device includes first and second word lines, a bit line, a source line, and a memory cell. The memory cell includes a spin-orbit torque (SOT) pattern having a first end electrically coupled to the source line, a magnetic tunnel junction pattern extending adjacent the SOT pattern, and a read transistor having a first current carrying terminal electrically coupled to a first end of the magnetic tunnel junction pattern, a second current carrying terminal electrically coupled to the bit line, and a gate terminal electrically coupled to the first word line. The memory cell also includes a write transistor having a first current carrying terminal electrically coupled to a second end of the SOT pattern, a second current carrying terminal electrically coupled to the first end of the magnetic tunnel junction pattern, and a gate terminal electrically coupled to the second word line.

公开(公告)号：US09524772B2

公开(公告)日：2016-12-20

申请号：US14793053

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Jongsun Park ,  Woong Choi

IPC: G11C5/06 ,  G11C7/06 ,  G11C5/14 ,  G11C7/02 ,  G11C8/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C2207/002

Abstract: A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Abstract translation: 存储器件包括包括单端位线结构的存储器单元的第一存储单元阵列，包括单端位线结构的存储单元的第二存储单元阵列，配置为输出所选择的位线的位线电压的参考电压发生器 的第一和第二存储单元阵列作为根据阵列选择信号的感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压;以及差分读出放大器，被配置为放大和输出感测电压 和参考电压。 感测电压和参考电压的逻辑状态彼此互补。