公开(公告)号：US20240332131A1

公开(公告)日：2024-10-03

申请号：US18448482

申请日：2023-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  Keumseok Park ,  Kang-Ill Seo

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0688 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices may include a power switch cell including an upper transistor on a substrate and a lower transistor between the substrate and the upper transistor. The upper transistor may include an upper channel region, first and second upper source/drain regions, and an upper gate electrode on the upper channel region. The lower transistor may include a lower channel region, first and second lower source/drain regions, and a lower gate electrode on the lower channel region. The first and second upper source/drain regions and the first and second lower source/drain regions may have the same conductivity type, the first upper source/drain region and the first lower source/drain region may be electrically connected to each other, the second upper source/drain region and the second lower source/drain region may be electrically connected to each other, and the upper and lower gate electrodes may be electrically connected to each other.

公开(公告)号：US20160056083A1

公开(公告)日：2016-02-25

申请号：US14833922

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  SANGHOON BAEK ,  SUNYOUNG PARK ,  SANG-KYU OH ,  JINTAE KIM ,  HYOSIG WON

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L29/417 ,  H01L21/321 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41758 ,  H01L29/66568

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract translation: 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在器件中比第一触点的顶表面的水平低的水平面上。

公开(公告)号：US20250132256A1

公开(公告)日：2025-04-24

申请号：US18603656

申请日：2024-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  PANJAE PARK ,  KANG-ILL SEO

IPC: H01L23/528 ,  H01L27/092

Abstract: CMOS devices are provided. A CMOS device includes a PMOS transistor and an NMOS transistor. Moreover, the CMOS device includes a dual power rail having a front-side power rail and a back-side power rail that are both coupled to one of the PMOS transistor or the NMOS transistor. The PMOS transistor and the NMOS transistor are in a vertical transistor stack, or are side-by-side.

公开(公告)号：US20210126014A1

公开(公告)日：2021-04-29

申请号：US16989160

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  HA-YOUNG KIM ,  SINWOO KIM ,  MOO-GYU BAE ,  JAEHA LEE

IPC: H01L27/11597 ,  H01L27/108

Abstract: Disclosed is a semiconductor device comprising a logic cell that is on a substrate and includes first and second active regions spaced apart from each other in a first direction, first and second active patterns that are respectively on the first and second active regions and extend in a second direction intersecting the first direction, gate electrodes extending in the first direction and running across the first and second active patterns, first connection lines that are in a first interlayer dielectric layer on the gate electrodes and extend parallel to each other in the second direction, and second connection lines that are in a second interlayer dielectric layer on the first interlayer dielectric layer and extend parallel to each other in the first direction.

公开(公告)号：US20210075406A1

公开(公告)日：2021-03-11

申请号：US16726379

申请日：2019-12-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JINTAE KIM ,  BYOUNGGON KANG ,  CHANGBEOM KIM ,  HA-YOUNG KIM ,  YONGEUN CHO

IPC: H03K3/037 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/423 ,  H01L29/06

Abstract: A semiconductor device includes a flip flop cell. The flip flop cell is formed on a semiconductor substrate, includes a flip flop circuit, and comprises a scan mux circuit, a master latch circuit, a slave latch circuit, a clock driver circuit, and an output circuit. Each of the scan mux circuit, the master latch circuit, the slave latch circuit, the clock driver circuit, and the output circuit includes a plurality of active devices which together output a resulting signal for that circuit based on inputs, is a sub-circuit of the flip flop circuit, and occupies a continuously-bounded area of the flip flop circuit from a plan view. At least a first sub-circuit and a second sub-circuit of the sub-circuits overlap from the plan view in a first overlap region, the first overlap region including part of a first continuously-bounded area for the first sub-circuit and part of a second continuously-bounded area for the second sub-circuit.

公开(公告)号：US20250022773A1

公开(公告)日：2025-01-16

申请号：US18492142

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd

Inventor： JINTAE KIM ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include an upper transistor including an upper channel region on a substrate, a lower transistor between the substrate and the upper transistor, the lower transistor including a lower channel region, and a power line extending longitudinally in a first horizontal direction. At least one of the upper channel region or the lower channel region may extend longitudinally in a second horizontal direction that traverses the first horizontal direction, and the at least one of the upper channel region or the lower channel region may overlap the power line in a thickness direction.

公开(公告)号：US20160056155A1

公开(公告)日：2016-02-25

申请号：US14833983

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-HO PARK ,  TAEJOONG SON ,  SANGHOON BAEK ,  JINTAE KIM ,  GIYOUNG YANG ,  HYOSIG WON

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0642 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract translation: 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。